Visible to Intel only — GUID: ldj1599621285513
Ixiasoft
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: ldj1599621285513
Ixiasoft
4.2. Functional Description
The PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 devices utilizes the I/O banks in Agilex™ 7 F-Series and I-Series devices. Each I/O bank has two I/O sub-banks in each device. The top sub-bank is placed near the edge of the die, and the bottom sub-bank is placed near the FPGA core.
Each sub-bank contains the following components:
- Hard memory controller
- I/O PLL and PHY clock trees
- DLL
- Input DQS/strobe trees
- 48 pins, organized into four I/O lanes of 12 pins each
Figure 51. Agilex™ 7 F-Series and I-Series I/O Bank Structure (Die Top View)This figure shows the I/O bank structure of the Agilex™ 7 F-Series and I-Series devices. The figure shows the view of the die as shown in the Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View". Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks and the locations of the SDM and HPS shared I/O banks for each device package.