PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

2.2.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices Top Level Interfaces

For E-Series devices, the PHY Lite for Parallel Interfaces Intel® FPGA IP consists of four top level RTL modules:

  • Clocks and reset (phylite_clocking)— includes PLL and clock phase alignment (CPA) circuitries.
  • Fabric (phylite_c2p_p2c_mapping)— maps connections between PHY Lite top-level ports and IO96 ports.
  • PHY data and control (phylite_lane)— includes core-to-periphery (C2P) and periphery-to-core (P2C) fabric adaptor (FA), PHY adaptor, Byte and Byte control. Each PHY Lite group corresponds to either one or two lanes. Depending on the configuration, one PHY Lite instance can have up to eight groups of single lane each or four groups of double lane each.
  • I/O (phylite_iobufs)— includes input and output buffers.
Figure 2. Top Level Diagram of the PHY Lite for Parallel Interfaces IP for E-Series Devices