PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

5.6.1.1. Design Example without Dynamic Reconfiguration

When the Enable dynamic reconfiguration option is not selected, Quartus® Prime software generates a design example of PHY Lite for Parallel Interfaces Intel® FPGA IP without a dynamic reconfiguration module.

This design example consists of simulation and synthesis design files.