PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces Intel® FPGA IP to One I/O Bank

You can instantiate multiple PHY Lite for Parallel Interfaces Intel® FPGA IPs within an I/O column. To constrain groups from separate PHY Lite for Parallel Interfaces Intel® FPGA IP instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies and the same voltage settings.