Visible to Intel only — GUID: bhc1410942038820
Ixiasoft
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: bhc1410942038820
Ixiasoft
6.3.2.1. Clock and Reset Interface Signals
Signal Name | Direction | Width | Description |
---|---|---|---|
ref_clk | Input | 1 | Reference clock for the PLL. The reference clock must be synchronous with strobe_in to ensure the dqs_enable signal is in-sync with strobe_in. |
reset_n | Input | 1 | Resets the interface. This signal is asynchronous. |
interface_locked | Output | 1 | Interface locked signal from PHY Lite for Parallel Interfaces Intel® FPGA IP to Intel® FPGA IP FPGA core. This signal indicates that the PLL and PHY circuitry are locked. Data transfer should starts after the assertion of this signal. |
core_clk_out | Output | 1 | Use this core clock in the core-to-periphery transfer of soft logic data and control signals. The core_clk_out frequency depends on the interface frequency and clock rate of user logic parameter. |
pll_extra_clock[0..3] | Output | 4 | These are the additional output clock signals generated by PHY Lite for Parallel Interfaces Intel® FPGA IP when you enable Specify additional output clocks based on existing PLL parameter.
Important: PHY Lite for Parallel Interfaces Intel® FPGA IP in Arria® 10 and Cyclone® 10 GX devices do not support exposing additional output clocks when VCO frequency is below 600 MHz.
|
pll_locked | Output | 1 | This is the locked signal for the additional output clocks generated by the IP. |