Arria® 10 FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your Intel® FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook
Intel Arria 10 Device Datasheet
Intel Arria 10 Device Overview
Intel Arria 10 GX/GT Device Errata and Design Recommendations
Intel Arria 10 Transceiver PHY User Guide
Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel Arria 10, and Intel® Stratix® 10 Devices
Intel FPGA I/O Phase-Locked Loop (Intel FPGA IOPLL) IP Core User Guide
Intel FPGA Chip ID IP Cores User Guide
Intel Arria 10 External Memory Interfaces IP User Guide
Intel Arria 10 External Memory Interfaces IP Design Example User Guide
Intel Arria 10 External Memory Interface IP Core Release Notes
Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
Intel FPGA Voltage Sensor IP Core User Guide
Early Power Estimator for Intel Arria 10 FPGAs User Guide
Intel FPGA Temperature Sensor IP Core User Guide
Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel FPGA Parallel Flash Loader IP Core User Guide
Intel FPGA ASMI Parallel II IP Core User Guide
Intel FPGA ASMI Parallel IP Core User Guide
Intel FPGA Remote Update IP Core User Guide
PHYLite Design Implementation Guidelines
AN 556: Using the Design Security Features in Intel FPGAs
AN 496: Using the Internal Oscillator IP Core
AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families
AN 756: Intel FPGA GPIO to Intel FPGA
AN 711: Power Reduction Features in Intel Arria 10 Devices
AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel Arria 10 Devices
AN 737: SEU Detection and Recovery in Intel Arria 10 Devices
AN 738: Intel Arria 10 Device Design Guidelines
AN 742: PMBus SmartVID Controller Reference Designs
AN 370: Using the Intel FPGA Serial Flash Loader with the Intel® Quartus® Prime Software

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Design Examples
Intel Arria10 Internal Temperature Sensor Reference Design
Intel Arria 10 IOPLL Multiple Profile Reconfiguration

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Training and Videos
Mitigating Single Event Upsets in Intel Arria 10 Devices
SEU Mitigation in Intel FPGA Devices: Hierarchy Tagging
Partial Reconfiguration for Intel Arria 10 Devices: Design Guidelines & Host Requirements
Partial Reconfiguration for Intel Arria 10 Devices: Introduction & Project Assignments
Partial Reconfiguration for Intel Arria 10 Devices: Output Files & Demonstration
Partial Reconfiguration for Intel Arria 10 Devices: PR IP Core & Project Flow
Advanced Signal Conditioning for Intel Arria 10 FPGA Transceivers
Building Interfaces with Intel Arria 10 High-Speed Transceivers
Generation 10 Transceiver Clocking
Transceiver Basics for 20 nm and 28 nm Devices
Intel Arria 10 Device Videos

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Development Kits
Intel Arria 10 GX FPGA Development Kit
Intel Arria 10 GX Transceiver Signal Integrity Development Kit
Intel Arria 10 SoC Development Kit
Intel® Programmable Acceleration Card (Intel® PAC) with Intel Arria 10 GX FPGA

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Intel FPGA Wiki
Intel Arria 10 LVDS Basic Design Examples
Intel Arria 10 Voltage Sensor

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2. Interface Protocols

Documentation

User Guides
External Memory Interface
Intel Arria 10 External Memory Interfaces IP User Guide
Intel Arria 10 External Memory Interfaces IP Design Example User Guide
Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide

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User Guides / Application Notes
Ethernet
Intel FPGA Triple-Speed Ethernet IP Core User Guide
Intel FPGA Low Latency Ethernet 10G MAC User Guide
Intel Arria 10 25 Gbps Ethernet IP Core User Guide
50 Gbps Ethernet IP Core User Guide
Low Latency 100-Gbps Ethernet IP Core User Guide
Low Latency 40-Gbps Ethernet IP Core User Guide
Intel Arria 10 Transceiver PHY User Guide
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design
AN 735: Intel FPGA Low Latency Ethernet 10G MAC IP Core Migration Guidelines
AN 808: Migration Guidelines from Intel Arria 10 to Intel Stratix 10 for 10G Ethernet Subsystem
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Intel Arria 10 Devices
AN 699: Using the Intel FPGA Ethernet Design Toolkit
AN 701: Scalable Low Latency Ethernet 10G MAC Using Intel Arria 10 1G/10G PHY
AN 794: Intel Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
AN 744: Scalable Triple Speed Ethernet Reference Design for Intel Arria 10 Devices

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User Guides
PCI Express*
Intel Arria 10 Hard IP for PCI Express* IP Cores
Intel Arria 10 and Intel Cyclone 10 Avalon® -ST Interface for PCIe* User Guide
Intel Arria 10 or Intel Cyclone 10 Avalon -MM DMA Interface for PCIe Solutions User Guide
Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe User Guide
Intel Arria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
Intel Arria 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

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Application Notes / Reference Design User Guide
PCI Express: Migrating to Intel Stratix 10 from Intel Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces
PCI Express DMA Reference Design Using External Memory
PCI Express High Performance Reference Design

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User Guides / Application Notes
Other Serial IP
JESD204B IP Core User Guide
RapidIO® II IP Core User Guide
AN 753: Intel FPGA JESD204B IP Core and ADI AD6676 Hardware Checkout Report
AN 749: Intel FPGA JESD204B IP Core and ADI AD9144 Hardware Checkout Report
AN 809: SerialLite III IP Core Feature and Interface Differences Between Intel Stratix 10, Intel Arria 10, and Intel Stratix V
Interlaken IP Core Feature and Interface Differences Between Intel Stratix 10, Intel Arria 10, and Intel Stratix V Devices

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User Guides
Digital Signal Processing (DSP)
LDPC IP Core User Guide
Intel FPGA_CORDIC IP Core User Guide
BCH IP Core USer Guide
FFT IP Core User Guide
FIR II IP Core User Guide
Viterbi IP Core User Guide
Turbo IP Core User Guide
Floating-Point IP Cores User Guide
High-Speed Reed-Solomon IP Core User Guide
Reed-Solomon II IP Core User Guide
NCO IP Core User Guide
Random Number Generator IP Core User Guide

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User Guides
Embedded
Embedded Peripherals IP User Guide

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User Guides
Audio and Video
Intel® FPGA SDI II IP Core User Guide

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Design Examples
External Memory Interface	Version
Intel Arria 10 DDR3 x40 with EMIF Debug Toolkit	15.0

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Design Example User Guides
Ethernet
25G Ethernet Design Example User Guide
50G Ethernet Design Example User Guide
Low Latency 100G Ethernet Design Example User Guide
Low Latency 40G Ethernet Example Design User Guide
Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Arria 10 Devices

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Design Example User Guides
PCI Express*
Intel Arria 10 and Intel Cyclone 10 Avalon-ST Hard IP for PCIe Design Example User Guide
Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe Design Example User Guide

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Design Example User Guides
Other Serial IP
JESD204B IP Core Design Example User Guide
Intel FPGA JESD204B Design Example User Guide for Intel Arria 10 Devices

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Training and Videos
External Memory Interface
Guide for New External Memory Interface (EMIF) Spec Estimator
External Memory Interface Device Selector Tutorial
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2
DDR4 Ping Pong PHY
How to Generate Intel Arria 10 EMIF Example Design
Creating Multiple Intel Arria 10 Memory Designs with Qsys
Simulating an Intel Arria 10 External Memory Interface
Intel Arria 10 FPGA & SoC EMIF
How to Implement Package Deskew in External Memory Interface Design in Intel Stratix 10 and Intel Arria 10
Board Timing for Intel Arria 10 EMIF IP
Implementing Over Constraint in Intel Arria 10 External Memory Interface
Automated Check of Intel FPGA External Memory Interfaces Board Layout Guidelines
Intel Arria 10 External Memory Interface Toolkit
Intel Arria 10 EMIF Example Traffic Generator
Using the Soft Nios® Processor to Debug Intel Arria 10 External Memory Interfaces
Intel Arria 10 External Memory Interface Read and Write 2-D Eye Diagram
External Memory Interface Driver Margining Part 1
External Memory Interface Driver Margining Part 2
How to Build RLDRAM3 EMIF Design for Arria 10 Development Kit and Test the Calibration Status Using EMIF Toolkit
Intel FPGA PHYLite Demo Part 1
Intel FPGA PHYLite Demo Part 2
Building Parallel Interfaces with Intel FPGA PHYLite IP
How to Perform Group Pin Placement for PHYLite IP
Generating PHYLite Example Design Simulation in ModelSim* in 16.1 with Intel Arria 10
How to Create the OCT Block for Calibrated Termination I/O Buffer in Intel FPGA PHYLIte IP
How to Estimate Inte Arria 10 / Intel Stratix 10 PHYLite Input and Output Path Latency
How to Configure A10 /S10 Intel FPGA PHYLite Input and Output Delay Constraints
How to Configure PHYLite IP Dynamic Reconfiguration Timing Settings
Introduction to Memory Interfaces IP in Intel Arria 10 & Intel Stratix 10 Devices
Integrating Memory Interfaces IP in Intel Arria 10 Devices
Verifying Memory Interfaces IP in Intel Arria 10 Devices
On-Chip Debugging of Memory Interfaces IP in Intel Arria 10 Devices

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Reference Designs
PCI Express*
PCIe* Avalon® Memory Host DMA Reference Design in Intel Arria 10 Part1
PCIe Avalon Memory Host DMA Reference Design in Intel Arria 10 Part2

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Quick Start Videos
Other Serial IP
Intel FPGA JESD204B IP Quick Start Video

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Intel FPGA Wiki
External Memory Interface
EMIF Device Selector
Intel Arria 10 Multiple EMIF Example Designs in Qsys
Board Skew Parameter Tool Guide
Intel Arria 10 EMIF Simulation Guidance
Generating and Modifying IBIS files for Intel Arria 10 EMIF
Calculating Channel Loss from DDRx Batch Wizard Results
Automated EMIF Layout Checks
Intel Arria 10 and Intel Stratix 10 EMIF Hardware Debug Guide
Intel Arria 10 Debugging Multiple EMIFs
Intel Arria 10 EMIF Debug GUI

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3. Design Planning

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Getting Started User Guide: Intel Quartus Prime Pro Edition
Platform Designer User Guide (Intel Quartus Prime Pro Edition)
DSP Builder for Intel FPGAs
AN 738: Intel Arria 10 Device Design Guidelines
AN 763: Intel Arria 10 SoC Device Design Guidelines

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Reference Designs
BluePrint Reference Design Part 1
BluePrint Reference Design Part 2

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Training and Videos
Fast & Easy I/O System Design with BluePrint
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2
Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2
Intel FPGA EMIF Resource and Pin Planning (AERP) Tool
Manage Device I/Os with the Pin Planner Tool in the Quartus® II Software

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Intel FPGA Wiki
Intel FPGA EMIF Resources and Pin Planning Tool
Intel Arria 10 Transceiver PHY Pin Planning

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4. Design Entry

Documentation

The Intel Quartus Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Intel Quartus Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these template, refer to the "Using Provided HDL Templates" section of the Intel Quartus Prime Pro Edition Handbook.

The Intel Quartus Prime design software also comes with Intel® High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for Intel FPGA products.

User Guides / Device Overview / Device Datasheet / White Paper
Design Recommendations User Guide: Intel Quartus Prime Pro Edition
Intel High Level Synthesis Compiler Getting Started Guide
Intel High Level Synthesis Compiler User Guide
Platform Designer User Guide: Intel Quartus Prime Pro Edition
Scripting User Guide: Intel Quartus Prime Pro Edition
Advanced Synthesis Cookbook
Intel High Level Synthesis Compiler Best Practices Guide
Intel High Level Synthesis Compiler Reference Manual
Intel High Level Synthesis Compiler Release Notes
Advanced Synthesis Cookbook
Applying the Benefits of Network on a Chip Architecture to FPGA System Design

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Design Examples
Platform Designer Design Examples
Platform Designer Pro Tutorial Design Example for Intel Arria 10 FPGA
Platform Designer Tutorial Design Example for Intel Arria 10 FPGA
Platform Designer Tutorial Design Example
VHDL Examples
Verilog Examples
Intel Quartus Design Examples

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Training and Videos
Using the Intel Quartus Prime Software: An Introduction
Introduction to Verilog HDL
Verilog HDL Basics
Advanced Verilog HDL Design Techniques
SystemVerilog with the Quartus II Software
VHDL Basics
Introduction to Platform Designer
Platform Designer in the Intel Quartus Prime Pro Edition Software
Creating a System Design with Platform Designer: Getting Started
Using Spectra-Q Synthesis in the Intel Quartus Prime Software

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Software Downloads
Download center for all versions of the Intel Quartus Prime software

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5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation
Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation
Simulation Quick-Start for ModelSim*-Intel FPGA Edition
Avalon® Verification IP Suite User Guide
Intel FPGA Software Installation and Licensing
Simulating the a8251 Model with the Visual IP Software
Simulating the a8259 Model with the Visual IP Software
Simulating the Reed-Solomon Model with the Visual IP Software
Simulating the Turbo Encoder/Decoder Model with the Visual IP Software
AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Intel Stratix 10 Devices
AN 720: Simulating the ASMI Block in Your Design
AN 351: Simulating Nios®II Processor Designs
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
Simulating Intel FPGA Devices with IBIS Models

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Design Examples
Avalon Verification IP Suite Design Example
Triple Rate SDI II Quad Instance Simulation/Compilation Design Example

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Training and Videos
Advanced System Design Using Qsys: System Verification with System Console
Advanced System Design Using Qsys: Component & System Simulation
Avalon® Verification Suite
Verifying Memory Interfaces IP in Intel Arria 10 Devices
Generating a Testbench with the Altera-ModelSim Simulation Tool
Simulation of SoC HPS DDR3 Core
How to Set Up RTL Simulations in Quartus, Qsys and Third Party Simulators
Ping Pong PHY DDR3 Simulation

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Intel FPGA Wiki
Simulating Designs with Lower-Level Qsys Systems
Intel Arria 10 EMIF Simulation Guidance
DDR4 Simulation Guidelines
Simpler Chaining DMA Testbench Example

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Software Downloads
Intel FPGA Development Tools
Intel Quartus Prime Software

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6. Implementation and Optimization

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Compiler User Guide: Intel Quartus Prime Pro Edition
Design Optimization User Guide: Intel Quartus Prime Pro Edition
Third-party Synthesis User Guide: Intel Quartus Prime Pro Edition
Design Constraints User Guide: Intel Quartus Prime Pro Edition
Block-Based Design User Guide: Intel Quartus Prime Pro Edition
Partial Reconfiguration User Guide: Intel Quartus Prime Pro Edition
DSP Builder for Intel FPGAs
AN 738: Intel Arria 10 Device Design Guidelines

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Training and Videos
Design Block Reuse in the Intel Quartus Prime Pro Software
Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Design Partitioning
Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Introduction
Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Timing Closure & Tips

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7. Timing Analysis

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Timing Analysis Overview
Timing Analyzer User Guide: Intel Quartus Prime Pro Edition
Quartus II Scripting Reference Manual
SDC and TimeQuest API Reference Manual
Intel Quartus Prime Timing Analyzer Cookbook
AN 366: Understanding I/O Output Timing for Intel FPGA Devices
AN 471: High-Performance FPGA PLL Analysis with TimeQuest
AN 433: Constraining and Analyzing Source-Synchronous Interfaces
AN 775: I/O Timing Information Generation Guidelines

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Design Examples
Timing Analyzer Design Examples

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Training and Videos
Getting Started with the TimeQuest Timing Analyzer
Intel® Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer
Intel® Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections
Intel® Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints
Intel® Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces
Intel® Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions
Timing Analysis: Lecture
Timing Analysis: Hands-on Labs
Intel® FPGA Timing Closure: Lecture
Intel® FPGA Timing Closure: Hands-On Lab

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Intel FPGA Wiki
Source Synchronous Interfaces between Intel FPGAs
Source Synchronous Analysis with TimeQuest
Constraining Edge Aligned Source Synch input interfaces in TimeQuest
Constraining Center Aligned Source Synchronous Input Interfaces in TimeQuest
TimeQuest User Guide
DDR Timing with TimeQuest

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8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Programmer User Guide: Intel Quartus Prime Pro Edition
Analyzing and Debugging Designs with System Console
Design Debugging Using In-System Sources and Probes
Debug Tools User Guide: Intel Quartus Prime Pro Edition
Intel FPGA Virtual JTAG (Intel FPGA_virtual_jtag) IP Core User Guide
Analyzing and Debugging Designs with System Console
FPGA-Adaptive Software Debug and Performance Analysis
System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug
ByteBlaster II Download Cable User Guide
Intel FPGA USB Download Cable User Guide
Intel FPGA Download Cable II User Guide
EthernetBlaster Communications Cable User Guide
BSDL Support
AN 827: Unified Tool for Generating Programming Files
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files
AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer
AN 799: Quick Intel Arria 10 Design Debugging Using Signal Probe and Rapid Recompile
AN 693: Remote Hardware Debugging over TCP/IP for Intel FPGA SoC
AN 541: SerialLite II Hardware Debugging Guide
AN 543: Debugging Nios II Software Using the Lauterbach Debugger
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
AN 624: Debugging with System Console over TCP/IP

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Design Examples
Intel Arria 10 DDR3 x40 with EMIF Debug Toolkit
Debugging with System Console over TCP/IP (SCTCP) Design Example
How to Debug HPS SPI Using SignalTap II

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Training and Videos
Debugging JTAG Chain Integrity
On-Chip Debugging of Memory Interfaces IP in Intel Arria 10 Devices
SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals
The Quartus® Software Debug Tools
JTAG Chain Debugger Tool
Quartus In Systems Sources and Probes Debug Flow
U-Boot Console and FDT Debug
Setting Up and Debugging Quartus Floating Licenses
Quartus II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs
Intel Arria 10 Temperature Sensor Debug
Using the Soft Nios® processor to Debug Intel Arria 10 External Memory Interfaces
How to Debug Intel FPGA Triple Speed Ethernet Link Synchronization Issue
Quick Signal Tapping with SignalProbe in the Intel FPGA Quartus II Software
Understanding and Utilizing USB Blaster and JTAG to Configure Intel FPGAs
Running the SoC Preloader with the ARM* DS-5* Debugger
Intel FPGA Transceiver Loopback with In-System Sources and Probes
Debugging Techniques for Qsys and Nios Based Bare Metal Systems

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Intel FPGA Wiki
Debug Apps
How to Debug HPS SPI Using SignalTap II
Development Boards and Kits
DisplayPort MegaCore Debug Checklist
System Console
Low Latency Ethernet 10G MAC Debug Checklist
SDI II MegaCore Debug Checklist
10Gbps Ethernet MAC Debug Checklist
Intel Arria 10 EMIF Debug GUI
Intel Arria 10 Debugging Multiple EMIFs

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Software Downloads
Intel FPGA Programming Software
Intel FPGA Jam™ STAPL Software
Cable and Adapter Drivers Information
MAX+PLUS® II Software
Intel FPGA Legacy Software
Intel Quartus Prime Software Stand-Alone Programmer
Intel FPGA Stand-Alone Programmer Software
Intel Quartus Prime Software

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Still Have Questions?

Get answers for the most common design issues.

Search the Knowledge Base

Explore Other Developer Centers

For other design guidelines, visit the following Developer Centers:

Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Altera® FPGAs and SoC FPGAs.
Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs.
FPGA Developer Center - Contains resources to complete your Altera® FPGA design.

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