Visible to Intel only — GUID: htp1524091712017
Ixiasoft
1.1. Generating Primary Device Programming Files
1.2. Generating Secondary Programming Files
1.3. Enabling Bitstream Security for Stratix® 10 and Agilex™ 7 Devices
1.4. Enabling Bitstream Encryption or Compression for Arria® 10 and Cyclone® 10 GX Devices
1.5. Generating Programming Files for Partial Reconfiguration
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems
1.7. Scripting Support
1.8. Generating Programming Files Revision History
2.1. Quartus® Prime Programmer
2.2. Programming and Configuration Modes
2.3. Basic Device Configuration Steps
2.4. Specifying the Programming Hardware Setup
2.5. Programming with Flash Loaders
2.6. Verifying the Programming File Source with Project Hash
2.7. Using PR Bitstream Security Verification ( Stratix® 10 Designs)
2.8. Stand-Alone Programmer
2.9. Programmer Settings Reference
2.10. Scripting Support
2.11. Using the Quartus® Prime Programmer Revision History
2.9.1. Device & Pin Options Dialog Box
2.9.2. More Security Options Dialog Box
2.9.3. Output Files Tab Settings (Programming File Generator)
2.9.4. Input Files Tab Settings (Programming File Generator)
2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator)
2.9.6. Configuration Device Tab Settings
2.9.7. Add Partition Dialog Box (Programming File Generator)
2.9.8. Add Filesystem Dialog Box (Programming File Generator)
2.9.9. Convert Programming File Dialog Box
2.9.10. Compression and Encryption Settings (Convert Programming File)
2.9.11. SOF Data Properties Dialog Box (Convert Programming File)
2.9.12. Select Devices (Flash Loader) Dialog Box
Visible to Intel only — GUID: htp1524091712017
Ixiasoft
1. Quartus® Prime Programmer User Guide
The Quartus® Prime Programmer allows you to program and configure Intel® CPLD, FPGA, and configuration devices. Following full design compilation, you generate the primary device programming files in the Assembler, and then use the Programmer to load the programming file to a device. This user guide details Intel® FPGA programming file generation and use of the Quartus® Prime Programmer.
Figure 1. Quartus® Prime Programmer
Section Content
Generating Primary Device Programming Files
Generating Secondary Programming Files
Enabling Bitstream Security for Stratix 10 and Agilex 7 Devices
Enabling Bitstream Encryption or Compression for Arria 10 and Cyclone 10 GX Devices
Generating Programming Files for Partial Reconfiguration
Generating Programming Files for Intel FPGA Devices with Hard Processor Systems
Scripting Support
Generating Programming Files Revision History