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1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
2.4. IP Core Generation Output ( Quartus® Prime Pro Edition)
2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor)
2.6. Simulating Intel® FPGA IP Cores
2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5.1. Register Map
5.2. Register Access Definition
5.3. Primary MAC Address
5.4. MAC Reset Control Register
5.5. TX Configuration and Status Registers
5.6. Flow Control Registers
5.7. Unidirectional Control Registers
5.8. RX Configuration and Status Registers
5.9. Timestamp Registers
5.10. ECC Registers
5.11. Statistics Registers
6.1. Clock and Reset Signals
6.2. Speed Selection Signal
6.3. Error Correction Signals
6.4. Unidirectional Signals
6.5. Avalon® Memory-Mapped Interface Programming Signals
6.6. Avalon® Streaming Data Interfaces
6.7. Avalon® Streaming Flow Control Signals
6.8. Avalon® Streaming Status Interface
6.9. PHY-side Interfaces
6.10. IEEE 1588v2 Interfaces
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1. About LL Ethernet 10G MAC
Updated for: |
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Intel® Quartus® Prime Design Suite 23.3 |
IP Version 22.0.3 |
The Low Latency (LL) Ethernet 10G (10GbE) Media Access Controller (MAC) Intel® FPGA IP core is a configurable component that implements the IEEE 802.3-2008 specification. To build a complete Ethernet subsystem in an Intel FPGA device and connect it to an external device, you can use the LL 10GbE Intel® FPGA IP core with an Intel FPGA PHY IP core or any of the supported PHYs.
The figure below shows a system with the LL 10GbE MAC Intel® FPGA IP core.
Figure 1. Typical Application of LL 10GbE MAC
Note: Intel FPGAs implement and support the LL 10GbE Media Access Control (MAC) and Multirate Ethernet PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T (1G/2.5G/5G/10Gb Ethernet) PHY standard devices. However, Intel FPGAs do not comply with or support these interface specifications to directly interface with the required twisted-pair copper cables such as CAT-5/6/7.
Section Content
Features
Release Information
Low Latency Ethernet 10G MAC Operating Modes
Device Family Support
Performance and Resource Utilization
Related Information