ASMI Parallel II Intel® FPGA IP User Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 18.0 |
| IP Version 18.0 |
The ASMI Parallel II Intel® FPGA IP provides access to the Intel FPGA configuration devices, which are the quad-serial configuration (EPCQ), low-voltage quad-serial configuration (EPCQ-L), and EPCQ-A serial configuration. You can use this IP to read and write data to the external flash devices for applications, such as remote system update and SEU Sensitivity Map Header File (.smh) storage.
Other than the features supported by the ASMI Parallel Intel® FPGA IP, the ASMI Parallel II Intel® FPGA IP additionally supports:
- Direct flash access (write/read) through the Avalon® memory-mapped interface.
- Control register for other operations through the control status register (CSR) interface in the Avalon® memory-mapped interface.
- Translate the generic commands from the Avalon® memory-mapped interface into device command codes.
The ASMI Parallel II Intel® FPGA IP is available for all Intel FPGA device families including the Intel® MAX® 10 devices which are using the GPIO mode.
The ASMI Parallel II Intel® FPGA IP only supports the EPCQ, EPCQ-L, and EPCQ-A devices. If you are using third-party flash devices, you must use the Generic Serial Flash Interface Intel® FPGA IP.
Note: The ASMI Parallel II Intel® FPGA IP is supported in the Intel® Quartus® Prime software version 17.0 and onwards.