ASMI Parallel Intel® FPGA IP Core User Guide

Download PDF
ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1. ASMI Parallel Intel® FPGA IP Core User Guide

Updated for:
Intel® Quartus® Prime Design Suite 18.0

The ASMI Parallel Intel® FPGA IP core provides access to erasable programmable configurable serial (EPCS), quad-serial configuration (EPCQ), low-voltage quad-serial configuration (EPCQ-L), and EPCQ-A serial configuration devices through parallel data input and output ports.

An EPCS device is a serial configuration device that you use to perform an active serial (AS) configuration on supported Intel devices.

An EPCQ/EPCQ-L/EPCQ-A device is a serial or quad-serial configuration that supports AS x1 or AS x4 configuration scheme. During AS configuration, the FPGA device is the master and the EPCS/EPCQ/EPCQ-L device is the slave. For the AS x1 and AS x4 configuration schemes, you must set the MSEL pins for the FPGA devices.

The ASMI Parallel Intel® FPGA IP core only supports the EPCS, EPCQ, EPCQ-L, and EPCQ-A devices. If you are using third-party flash devices, refer to the Generic Serial Flash Interface Intel® FPGA IP Core User Guide.

The ASMI Parallel Intel® FPGA IP core implements a basic active serial memory interface (ASMI). To use this IP core, you do not need to know the details of the serial interface and the read and write protocol of an EPCS/EPCQ/EPCQ-L/EPCQ-A device.

The memory in the EPCS/EPCQ/EPCQ-L/EPCQ-A device contains two sections:

  • Configuration memory—contains the bitstream of the configuration data
  • General purpose memory—used for an application-specific storage

You can perform the following tasks with the ASMI Parallel Intel® FPGA IP core:

  • Read the EPCS silicon identification (device identification)
  • Protect a certain sector in the EPCS/EPCQ/EPCQ-L/EPCQ-A device from write or erase
  • Read the data at a specified address from the EPCS/EPCQ/EPCQ-L/EPCQ-A device
  • Perform single-byte write to the EPCS/EPCQ/EPCQ-L/EPCQ-A device
  • Perform page write to the EPCS/EPCQ/EPCQ-L/EPCQ-A device
  • Read the status of the EPCS/EPCQ/EPCQ-L/EPCQ-A device
  • Erase a specified sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A device
  • Erase a specified die on the EPCQ-L512 and EPCQ-L1024
  • Erase memory in bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-L512/EPCQ-A device

This figure shows that you can use the ASMI Parallel Intel® FPGA IP core to access the general purpose memory portion of the EPCS/EPCQ/EPCQ-L/EPCQ-A devices through the supported FPGA devices.

CAUTION:
Intel® recommends you to be cautious when accessing the general purpose memory in the configuration devices to avoid corrupting the configuration bits in the configuration memory.
Figure 1. Accessing the General Purpose Memory in the Configuration Devices using the ASMI Parallel Intel® FPGA IP Core

Section Content
Device Family Support
Ports and Parameters
Installing and Licensing Intel FPGA IP Cores
ASMI Parallel Intel FPGA IP Core Operations and Timing Requirements
ASMI Parallel Intel FPGA IP Core User Guide Archives
Document Revision History for ASMI Parallel Intel FPGA IP Core User Guide

Related Information
Level Two Title