Intel® FPGA Design Examples
Intel® design examples provide efficient solutions for common design challenges. These designs can be used as a starting point for developing with your unique system and are available using many functions such as filters, arithmetic functions, error detection/correction, modulation/demodulation, and video and image processing.
Design examples are also available in the Design Store for Intel® FPGAs and RocketBoards.org.
Search Altera content collection of development guides, training, software downloads and software kits for FPGA.
10/30/2023
Interface Protocols Design Examples | Intel
Intel provides a variety of ready-to-use design samples like the Interface Protocols Design Examples to deliver efficient solutions for your application.
Discover download files, system requirements, and support information for the Serial RapidIO (SRIO) Interoperability with TI DSP 6482 reference design.
9/7/2023
MAX II Design Examples | Intel
MAX II and MAX CPLD Design Examples demonstrate various features of the MAX II and MAX low-power CPLD families using Quartus II or MAX+PLUS II software.
Discover download files, system requirements, and support information for the FPGA Design Security Solution Using a Secure Memory Device reference design.
Discover download files, system requirements and features for the Serial RapidIO to TI 6482 DSP reference design in this guide from the Intel support team.
The Intel drive-on-a-chip motor control reference design is an integrated drive system on a single Cyclone V SoC or Intel MAX 10. Learn more in this guide.
OpenCL Mandelbrot Fractal Algorithm example provides a kernel that implements the Mandelbrot fractal algorithm as well as a host application that displays the results to the screen.
Single-Port Triple-Speed Ethernet On-Board PHY Chip datapath reference design provides a simple and quick way to implement your own Ethernet-based design in an Intel FPGA.
Intel offers a PCI Express (PCIe*) to External Memory reference design that demonstrates the operation of PCIe-based MegaCore function with a DDR2 or DDR3 SDRAM memory controller.
10-Gbps Ethernet Hardware Demonstration reference design provides a quick way to implement your 10-Gbps Ethernet (10GbE)-based design in an Intel FPGA.
This example describes a 64 bit x 8 bit synchronous, true dual-port RAM design with any combination of independent read or write operations in the same clock cycle in VHDL.