Intel® FPGA Design Examples
Intel® design examples provide efficient solutions for common design challenges. These designs can be used as a starting point for developing with your unique system and are available using many functions such as filters, arithmetic functions, error detection/correction, modulation/demodulation, and video and image processing.
Design examples are also available in the Design Store for Intel® FPGAs and RocketBoards.org.
6/25/2025
Altera® FPGA Design Examples | Altera
Search Altera content collection of development guides, training, software downloads and software kits for FPGA.
9/7/2023
MAX II Design Examples | Intel
MAX II and MAX CPLD Design Examples demonstrate various features of the MAX II and MAX low-power CPLD families using Quartus II or MAX+PLUS II software.
Discover download files, system requirements, and support information for the FPGA Design Security Solution Using a Secure Memory Device reference design.
The Intel drive-on-a-chip motor control reference design is an integrated drive system on a single Cyclone V SoC or Intel MAX 10. Learn more in this guide.
Single-Port Triple-Speed Ethernet On-Board PHY Chip datapath reference design provides a simple and quick way to implement your own Ethernet-based design in an Intel FPGA.
10-Gbps Ethernet Hardware Demonstration reference design provides a quick way to implement your 10-Gbps Ethernet (10GbE)-based design in an Intel FPGA.
6/12/2023
Serial Design Examples | Intel
Intel provides a variety of ready-to-use design samples like the Interface Serial Design Examples to deliver efficient solutions for your application.
6/12/2023
Ethernet Design Examples | Intel
Intel provides a variety of ready-to-use design samples like the Ethernet Design Examples to deliver efficient solutions for your application.
This template shows how to infer digital signal processing (DSP) blocks with different features from VHDL code. Recommended for Stratix III and Stratix IV FPGA devices.
This example describes a 16-bit binary adder tree in VHDL. Devices with 4-input lookup tables in logic elements (LEs) can improve performance with a binary adder tree structure.
This example describes a two-input, 8 bit adder/subtractor design in VHDL. The design unit dynamically switches between add and subtract operations.
The VHDL 8x64 Shift Register with Taps example describes an 8-bit wide, 64-bit long shift register with equally spaced taps in VHDL. Learn more from Intel.