Stratix® 10 FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your Intel® FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

Agilex™ 7 Design Hub Stratix® 10 Developer Center Arria® 10 Developer Center Cyclone® 10 Developer Center MAX® 10 Developer Center

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Intel® Stratix® 10 GX/SX Device Overview

Intel® Stratix 10 Device Datasheet

Intel Stratix 10 GX, MX, and SX Device Family Pin Connection Guidelines

Intel Stratix 10 Clocking and PLL User Guide

Intel Stratix 10 Configuration User Guide

Intel Stratix 10 General Purpose I/O User Guide

Intel Stratix 10 High-Speed LVDS I/O User Guide

Intel Stratix 10 JTAG Boundary-Scan Testing User Guidex

Intel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide

Intel Stratix 10 Power Management User Guide

Intel Stratix 10 SEU Mitigation User Guide

Intel Stratix 10 Analog to Digital Converter User Guide

Intel Stratix 10 Device Design Guidelines

Intel Stratix 10 Embedded Memory User Guide

Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide

Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide

Intel Stratix 10 MX (DRAM System-in-Package) Device Overview

Mailbox Client Intel Stratix 10 FPGA IP Core User Guide

AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Devices

AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage
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Training and Videos

Configuration for Intel® Stratix® 10 Devices

Intel® Stratix 10 Transceiver Basics
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Development Kits

Intel® Stratix® 10 GX FPGA Development Kit

Intel® Stratix 10 GX Signal Integrity Development Kit

Intel® Stratix 10 SX SoC Development Kit
Intel® Stratix® 10 TX Signal Integrity Development Kit
Intel® Stratix® 10 MX FPGA Development Kit
Intel® Stratix® 10 DX FPGA Development Kit
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Intel FPGA Wiki

Intel® Arria® 10 and Intel® Stratix® 10 EMIF Hardware Debug Guide
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2. Interface Protocol

Documentation

User Guides
External Memory Interfaces

Intel® Stratix® 10 External Memory Interfaces IP User Guide

Intel Stratix 10 External Memory Interfaces IP Design Example User Guide

Intel Stratix 10 MX HBM2 IP User Guide

Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide
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User Guides / Application Notes
Ethernet User Guides

Intel® FPGA Triple-Speed Ethernet IP Core User Guide

Intel FPGA Low Latency Ethernet 10G MAC User Guide

Intel Stratix® 10 1G/2-5G/5G/10G Multi-Rate Ethernet PHY IP Core User Guide

Intel Stratix 10 10GBASE-KR PHY IP Core User Guide

Intel® Stratix 10 Low Latency 40-Gbps Ethernet IP Core User Guide

Intel Stratix 10 Low Latency 100-Gbps Ethernet IP Core User Guide

Intel Stratix 10 E-Tile Transceiver PHY User Guide

Intel Stratix 10 H-Tile Hard IP for Ethernet IP Core User Guide

AN 735: Altera® Low Latency Ethernet 10G MAC IP Core Migration Guidelines

AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix 10 for 10G Ethernet Subsystem

AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design
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User Guides
PCI Express*

Intel® Stratix® 10 Avalon®-MM Interface for PCIe* Solutions User Guide

Intel Stratix 10 Avalon-ST and Single Root I/O Virtualization (SRIOV) Interface for PCIe Solutions User Guide

Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide
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Application Notes
Other Serial IP

AN 782: Interlaken IP Core Feature and Interface Differences Between Stratix® 10, Arria® 10, and Stratix V Devices

AN 804: Implementing ADC- Intel® Stratix 10 Multi-Link Design with JESD204B RX IP Core

AN 809: SerialLite III IP Core Feature and Interface Differences Between Stratix 10, Arria 10, and Stratix V
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User Guides
Transceiver PHY

Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide
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User Guides
Digital Signal Processing (DSP)

LDPC IP Core User Guide

Intel FPGA_CORDIC IP Core User Guide

BCH IP Core User Guide

FFT IP Core User Guide

FIR II IP Core User Guide

Viterbi IP Core User Guide

Turbo IP Core User Guide

Fixed-Point IP Cores (ALTERA_FIXEDPOINT_FUNCTIONS) User Guide

High-Speed Reed-Solomon IP Core User Guide

NCO IP Core User Guide

Random Number Generator IP Core User Guide
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User Guides
Embedded

Intel® FPGA SDI II IP Core User Guide
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User Guides
Audio and Video

Embedded Peripherals IP User Guide
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Design Example User Guides
Ethernet

Intel® Stratix® 10 Low Latency 100G Ethernet Design Example User Guide

Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Stratix 10 Devices

Intel® Stratix 10 Low Latency 40G Ethernet Design Example User Guide

Intel Stratix 10 H-Tile Hard IP for Ethernet Design Example User Guide
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Design Example User Guides
PCI Express*

Intel® Stratix® 10 Avalon®-MM Hard IP for PCIe* Design Example User Guide

Intel Stratix 10 Avalon-ST Hard IP for PCIe Design Example User Guide
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Design Example User Guides
Other Serial IP

Interlaken IP Core (2nd Generation) Design Example User Guide

Intel® FPGA JESD204B Design Example User Guide for Intel Stratix® 10 Devices

JESD204B IP Core Design Example User Guide

SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices
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Training and Videos
External Memory Interface

Guide For New External Memory Interface (EMIF) Spec Estimator

Intel® Stratix® 10 External Memory Interface Design Guidelines

Intel® Stratix 10 External Memory Interface Guidelines

DDR4 Ping Pong PHY

How to Implement Package Deskew in External Memory Interface Design in Intel® Stratix 10 and Intel® Arria® 10

Intel Stratix 10 External Memory Interface EMIF Calibration Debug Guide

Automated Check of Altera® External Memory Interfaces Board Layout Guidelines

How to Estimate Intel® Arria 10 / Intel® Stratix 10 PHYLite Input and Output Path Latency

How to Configure Intel® Arria 10 / Intel® Stratix 10 Altera PHYLITE Input and Output Delay Constraints

Introduction to Memory Interfaces IP in Intel® Arria 10 & Intel® Stratix 10 Devices

High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX Devices: Introduction, Architecture

High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX Devices: HBMC Features

High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX Devices: Implementation
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Quick Start Videos
Other Serial IP
Intel FPGA JESD204B IP Quick Start Video
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Intel FPGA Wiki
External Memory Interface

EMIF Device Selector

Intel® Stratix® 10 HBM2

Intel® Arria® 10 and Intel® Stratix 10 EMIF Hardware Debug Guide

Intel® Stratix 10 EMIF Debug GUI

Board Skew Parameter Tool Guide

Automated EMIF Layout Checks
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Reference Designs
PCI Express*

Reference Design: Gen3x8 AVMM DMA - Stratix® 10
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3. Design Planning

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Getting Started User Guide: Intel® Quartus® Prime Pro Edition

Platform Designer User Guide: Intel Quartus Prime Pro Edition

DSP Builder for Intel® FPGAs

Intel Stratix® 10 Device Design Guidelines

AN 821: Interface Planning for Intel Stratix 10 FPGAs
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Design Examples

BluePrint Reference Design Part 1

BluePrint Reference Design Part 2
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Training and Videos

Fast & Easy I/O System Design with Interface Planner

Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2

Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2

AERP - Intel FPGA EMIF (External Memory Interfaces) Resources and Pin Planning Tool
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Intel FPGA Wiki

Intel FPGA EMIF Resources and Pin Planning Tool

Intel® Stratix® 10 EMIF Device Selector
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4. Design Entry

Documentation

The Intel® Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

Verilog

VHDL

The Intel Quartus Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Intel Quartus Prime Pro Handbook.

The Intel® Quartus® Prime design software also comes with Intel® High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for Intel® FPGA products.

User Guides / Device Overview / Device Datasheet / White Paper

Design Recommendations User Guide: Intel Quartus Prime Pro Edition

Intel High Level Synthesis Compiler Getting Started Guide

Intel High Level Synthesis Compiler User Guide

Scripting User Guide: Intel Quartus Prime Pro Edition

Advanced Synthesis Cookbook

Intel High Level Synthesis Compiler Best Practices Guide

Intel High Level Synthesis Compiler Reference Manual

Intel High Level Synthesis Compiler Release Notes

Applying the Benefits of Network on a Chip Architecture to FPGA System Design
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Design Examples

Platform Designer Design Examples

Platform Designer Pro Tutorial Design Example for Intel® Arria® 10 FPGA (.zip)

Platform Designer Tutorial Design Example for Intel Arria 10 FPGA (.zip)

Platform Designer Tutorial Design Example (.zip)

VHDL Examples

Verilog Examples

Quartus® Design Examples
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Training and Videos

Using the Quartus® Prime Software: An Introduction

Introduction to Verilog HDL

Verilog HDL Basics

Advanced Verilog HDL Design Techniques

SystemVerilog with the Quartus II Software

VHDL Basics

Introduction to Platform Designer

Platform Designer in the Intel® Quartus Prime Pro Edition Software

Creating a System Design with Platform Designer: Getting Started

Using Spectra-Q Synthesis in the Quartus Prime Software
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Software Downloads

Download center for all versions of the Intel® Quartus® Prime software
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5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

Simulation Quick-Start for ModelSim*-Intel® FPGA Edition

Avalon® Verification IP Suite User Guide

Intel FPGA Software Installation and Licensing

Simulating the a8251 Model with the Visual IP Software

Simulating the a8259 Model with the Visual IP Software

Simulating the Reed-Solomon Model with the Visual IP Software

Simulating the Turbo Encoder/Decoder Model with the Visual IP Software

AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Intel Stratix® 10 Devices

AN 351: Simulating Nios® II Processor Designs

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

Simulating Intel FPGA Devices with IBIS Models
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Design Examples
Avalon® Verification IP Suite Design Example
Triple Rate SDI II Quad Instance Simulation/Compilation Design Example
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Training and Videos

Advanced System Design Using Qsys: System Verification with System Console

Advanced System Design Using Qsys: Component & System Simulation

Avalon® Verification Suite

Verifying Memory Interfaces IP in Arria® 10 Devices

Generating a Testbench with the Altera-ModelSim Simulation Tool

Simulation of SoC HPS DDR3 Core

How to Set Up RTL Simulations in Quartus, Qsys and Third Party Simulators

Ping Pong PHY DDR3 Simulation
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Intel FPGA Wiki

Simulating Designs with Lower-Level Qsys Systems

DDR4 Simulation Guidelines

Simpler Chaining DMA Testbench Example
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Software Downloads

Intel Quartus® Software
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6. Implementation and Optimization

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Compiler User Guide: Intel Quartus Prime Pro Edition

Design Optimization User Guide: Intel Quartus Prime Pro Edition

Third-party Synthesis User Guide: Intel Quartus Prime Pro Edition

Design Constraints User Guide: Intel Quartus Prime Pro Edition

Block-Based Design User Guide: Intel Quartus Prime Pro Edition

Partial Reconfiguration User Guide: Intel Quartus Prime Pro Edition

DSP Builder for Intel® FPGAs

Intel Stratix® 10 High-Performance Design Handbook

Intel Stratix 10 Device Datasheet

Intel Stratix 10 Device Design Guidelines

AN 716: Hyper-Optimization for Stratix 10 Designs

AN 715: Hyper-Pipelining for Stratix 10 Designs
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Training and Videos

Introduction to Hyper-Retiming

Eliminating Barriers to Hyper-Retiming

Introduction to Incremental Compilation

Incremental Block-Based Compilation in the Intel® Quartus® Prime Pro Software: Introduction

Incremental Block-Based Compilation in the Quartus Prime Pro Software: Design Partitioning

Advanced Optimization with Intel Stratix 10 FPGA Hyperflex™ Architecture

Hyper-Optimization Techniques 1: Loop Analysis and Solutions

Hyper-Optimization Techniques 2: Pre-Computation

Hyper-Optimization Techniques 3: Shannon’s Decomposition

Introduction to Hyper-Optimization

Intel Quartus Prime Software Hyper-Aware Design Flow

Introduction to Hyper-Pipelining

Performance Optimization with Intel Stratix 10 FPGA Hyperflex Architecture

Intel® Stratix 10 Hyperflex Design: Analyzing Critical Chains

The Intel Hyperflex FPGA Optimization Workshop

Using Fast Forward Compile for the Intel Hyperflex Architecture
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7. Timing Analysis

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Timing Analysis Overview

Timing Analyzer User Guide (Intel® Quartus® Prime Pro Edition)

Quartus II Scripting Reference Manual

SDC and TimeQuest API Reference Manual

Intel Quartus Prime Timing Analyzer Cookbook

AN 366: Understanding I/O Output Timing for Altera® Devices

AN 471: High-Performance FPGA PLL Analysis with TimeQuest

AN 433: Constraining and Analyzing Source-Synchronous Interfaces

AN 775: I/O Timing Information Generation Guidelines
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Design Examples

Timing Analyzer Design Examples
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Training and Videos

Getting Started with the TimeQuest Timing Analyzer
Intel® Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer
Intel® Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections
Intel® Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints
Intel® Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces
Intel® Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions
Timing Analysis: Lecture
Timing Analysis: Hands-on Labs
Intel® FPGA Timing Closure: Lecture
Intel® FPGA Timing Closure: Hands-On Lab
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Intel FPGA Wiki

Source Synchronous Interfaces between Intel FPGA FPGAs

Source Synchronous Analysis with TimeQuest

Constraining Edge Aligned Source Synch input interfaces in TimeQuest

Constraining Center Aligned Source Synchronous Input Interfaces in TimeQuest

TimeQuest User Guide

DDR Timing with TimeQuest
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8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Programmer User Guide: Intel Quartus Prime Pro Edition

Analyzing and Debugging Designs with System Console

Design Debugging Using In-System Sources and Probes

Debug Tools User Guide: Intel Quartus Prime Pro Edition

Intel FPGA Virtual JTAG (Intel FPGA_virtual_jtag) IP Core User Guide

Analyzing and Debugging Designs with System Console

FPGA-Adaptive Software Debug and Performance Analysis

System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug

ByteBlaster II Download Cable User Guide

Intel FPGA USB Download Cable User Guide

Intel FPGA Download Cable II User Guide

EthernetBlaster Communications Cable User Guide

BSDL Support

AN 827: Unified Tool for Generating Programming Files

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files

AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer

AN 693: Remote Hardware Debugging over TCP/IP for Intel FPGA SoC

AN 541: SerialLite II Hardware Debugging Guide

AN 543: Debugging Nios II Software Using the Lauterbach Debugger

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

AN 624: Debugging with System Console over TCP/IP
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Design Examples

Intel® Arria® 10 DDR3 x40 with EMIF Debug Toolkit

Debugging with System Console over TCP/IP (SCTCP) Design Example

How to Debug HPS SPI Using SignalTap II

Intel® MAX® 10 DDR3 Design with Debug Feature

Intel® MAX® 10 LPDDR2 Design with Debug Feature

PCIe* In-Simulation Status Debug for PIPE Interface

Remote System Debug

System Console Debugging
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Training and Videos

Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction

Debugging JTAG Chain Integrity

On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices

SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals

The Quartus® Software Debug Tools

JTAG Chain Debugger Tool

Quartus In Systems Sources and Probes Debug Flow

U-Boot Console and FDT Debug

Setting Up and Debugging Quartus Floating Licenses

Quartus II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs

Intel® Arria 10 Temperature Sensor Debug

Using the Soft Nios® processor to Debug Arria 10 External Memory Interfaces

How to Debug Altera® Triple Speed Ethernet Link Synchronization Issue

Quick Signal Tapping with SignalProbe in the Altera Quartus II Software

Understanding and Utilizing USB Blaster and JTAG to Configure Intel FPGAs

Running the SoC Preloader with the ARM* DS-5* Debugger

Altera Transceiver Loopback with In-System Sources and Probes

Debugging Techniques for Qsys and Nios Based Bare Metal Systems
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Intel FPGA Wiki

Debug Apps

How to Debug HPS SPI Using SignalTap II

Development Boards and Kits

DisplayPort MegaCore Debug Checklist

System Console

Low Latency Ethernet 10G MAC Debug Checklist

SDI II MegaCore Debug Checklist

10Gbps Ethernet MAC Debug Checklist

Intel® Arria® 10 EMIF Debug GUI

Intel® Arria 10 Debugging Multiple EMIFs
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Software Downloads

Intel FPGA Programming Software

Intel FPGA Jam™ STAPL Software

Cable and Adapter Drivers Information

MAX+PLUS® II Software

Intel FPGA Legacy Software

Intel Quartus® Prime Software Stand-Alone Programmer

Intel FPGA Stand-Alone Programmer Software

Intel Quartus Prime Software
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