AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

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ID 683231
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines x
1.1. Implementing the Altera PHYLite Design 1.2. Mapping the Interface Signals 1.3. Performance Comparison 1.4. Use Case Examples 1.5. Altera GPIO to Altera PHYLite Design Example 1.6. Document Revision History
1.1. Implementing the Altera PHYLite Design x
1.1.1. Parameter Settings
1.4. Use Case Examples x
1.4.1. Use Case 1: Source Synchronous I/O Interface 1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device 1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces 1.4.4. Use Case 4: GPIO Interface Using 3.0V/2.5V I/O Standard 1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
1.5. Altera GPIO to Altera PHYLite Design Example x
1.5.1. Simulation Diagrams 1.5.2. Design Verification
1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

Intel offers the Altera PHYLite for Parallel Interfaces IP core as an alternative solution for the Altera GPIO IP core for high speed applications that fail to close timing.

The Altera PHYLite for Parallel Interfaces IP core (or Altera PHYLite IP core) enables your design to achieve better timing performance. Intel recommends that you use the Altera PHYLite IP core for general purpose I/O (GPIO) data rates higher than 200 Mbps to achieve optimal out signal.

Note:

Switching an Altera GPIO design to the Altera PHYLite IP core is very resource intensive.

  • The Altera PHYLite IP core uses up the IOPLL, the phy_clk network, in the particular I/O bank.
  • You may not be able to use the external memory interfaces and the Altera PHYLite IP core as normal memory protocols in this I/O bank unless they operate at the frequency multiplication of the Altera GPIO interface being switched.
  • You also cannot use the Altera LVDS SERDES IP core in the same I/O bank with Altera PHYLite IP core.
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