AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
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Document Table of Contents
Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

This reference design demonstrates the Low Latency Ethernet 10G IP solution for Arria® 10 devices.

This design uses Intel's Low Latency Ethernet 10G Media Access Controller (MAC) and XAUI PHY IP cores with a dual XAUI small form factor pluggable plus (SFP+) high-speed mezzanine card (HSMC) board and FPGA mezzanine card (FMC) to high-speed mezzanine card (HSMC) adapter board on Arria® 10 FPGA development kit.

The design provides flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopback at various points.

This design offers the following features:
  • Loopback points that include XGMII and serial physical medium attachment (PMA) interface in the Arria® 10 FPGA development board, and PMA interface in the Broadcom PHY BCM8727 chip on the Dual XAUI to SFP+ HSMC board.
  • External optical loopback test at HSMC board SFP+ modules.
  • Sequential random bursts tests. You can configure the number of packets, payload-data type, and payload size for each burst.
  • Packet statistics for traffic generator, monitor, MAC transmitter (TX) and MAC receiver (RX).
  • Packet classification for different frame sizes transmitted and received by the MAC.
  • Throughput for the traffic received by the traffic monitor.
  • System Console user interface. This TCL-based user interface allows you to dynamically configure and monitor any registers in the reference design.
Figure 1. System Architecture OverviewThis figure shows the high-level overview of the design's system architecture.
Figure 2. Ethernet Subsystem Clocking SchemeThis figure shows the clocking scheme for the Ethernet subsystem.
Figure 3. Design Top Level Reset SchemeThis figure shows the reset scheme. Use the master reset signal (csr_rst_n) to reset the MAC, PHY, MDIO, address decoder, reset synchronizer, and synchronizer. This signal connects to hard reset button.

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