MAX® 10 FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your Intel® FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

Agilex™ 7 Design Hub Stratix® 10 Developer Center Arria® 10 Developer Center Cyclone® 10 Developer Center MAX® 10 Developer Center

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Intel® MAX® 10 FPGA Device Datasheet

Intel MAX 10 Clocking and PLL User Guide

Intel MAX 10 Analog to Digital Converter User Guide

Intel MAX 10 FPGA Device Overview

Intel MAX 10 General Purpose I/O User Guide

Intel MAX 10 High-Speed LVDS I/O User Guide

Intel MAX 10 FPGA Configuration User Guide

Intel MAX 10 Power Management User Guide

Intel MAX 10 Embedded Memory User Guide

Intel MAX 10 FPGA Device Architecture

Intel MAX 10 User Flash Memory User Guide

Intel MAX 10 FPGA Signal Integrity Design Guidelines

Intel MAX 10 FPGA Device Family Pin Connection Guidelines

Intel MAX 10 FPGA Design Guidelines

Intel FPGA Parallel Flash Loader IP Core User Guide

Intel FPGAs Remote Update IP Core User Guide

AN 286: Implementing LED Drivers in Intel FPGAs MAX Series

AN 773: Drive-On-Chip Reference Design for Intel MAX 10 Devices

AN 100: In-System Programmability Guidelines

AN 265: Using Intel FPGAs MAX Series as Microcontroller I/O Expanders

AN 294: Crosspoint Switch Matrices in Intel FPGAs MAX Series

AN 425: Using the Command-Line Jam STAPL Solution for Device Programming

AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

AN 486: SPI to I2C Using Intel FPGAs MAX Series

AN 488: Stepper Motor Controller Using Intel FPGAs MAX Series

AN 490: Intel FPGAs MAX Series as Voltage Level Shifters

AN 491: Power Sequence Auto Start Using Intel FPGAs MAX Series

AN 492: CF+ Interface Using Intel FPGAs MAX Series

AN 493: I2C Battery Gauge Interface Using Intel FPGAs MAX Series

AN 494: GPIO Pin Expansion Using I2C Bus Interface in Intel FPGAs MAX Series

AN 495: IDE/ATA Controller Using Intel FPGAs MAX Series

AN 496: Using the Internal Oscillator IP Core

AN 498: LED Blink Using Power Sequencing in Intel FPGAs MAX Series

AN 500: NAND Flash Memory Interface with Intel FPGAs MAX Series

AN 501: Pulse Width Modulation Using Intel FPGAs MAX Series

AN 502: Implementing SMBus Controller in Intel FPGAs MAX Series

AN 509: Multiplexing SDIO Devices Using Intel FPGAs MAX Series

AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families

AN 630: Real-Time ISP and ISP Clamp for Intel FPGAs MAX Series

AN 631: Replacing Serial EEPROMs with User Flash Memory in Intel FPGAs MAX Series

AN 741: Remote System Upgrade for Intel MAX 10 FPGA Devices over UART with the Nios® II Processor

AN 752: Guidelines for Handling Intel FPGAs Wafer Level Chip Scale Package (WLCSP)

AN 370: Using the Intel FPGA Serial Flash Loader with the Intel® Quartus® Prime Software
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Design Examples

Intel MAX 10 FPGA Design Examples on Design Store
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Training and Videos

Integrating an Analog-to-Digital Converter in Intel MAX 10 Devices

Introduction to Analog-to-Digital Conversion in Intel MAX 10 Devices

Introduction to Remote System Upgrade in Intel MAX 10 Devices

Remote System Upgrade in Intel® MAX® 10 Devices

Using the ADC Toolkit in Intel MAX 10 Devices

Using the Intel MAX 10 User Flash Memory with the Nios II Processor

Using the Intel MAX 10 User Flash Memory

Intel MAX 10 FPGA Videos
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Development Kits

Intel MAX 10 FPGA Development Kit User Guide

Intel MAX 10 FPGA 10M50 Evaluation Kit User Guide

Intel MAX 10 FPGA (10M08S, 144-EQFP) Evaluation Kit User Guide
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Intel FPGA Wiki

Intel MAX 10 On-Chip Flash IP Read Operation Example
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2. Interface Protocols

Documentation

User Guides / Device Overview / Device Datasheet
External Memory Interface

Intel MAX 10 External Memory Interface User Guide

External Memory Interfaces IP Support Center
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User Guides / Application Notes
Ethernet

Intel FPGA Triple-Speed Ethernet IP Core User Guide
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User Guides
DSP

LDPC IP Core User Guide

ALTERA_CORDIC IP Core User Guide

BCH IP Core User Guide

FFT IP Core User Guide

FIR II IP Core User Guide

Viterbi IP Core User Guide

Turbo IP Core User Guide

High-Speed Reed-Solomon IP Core User Guide

Reed-Solomon II IP Core User Guide

NCO IP Core User Guide

Random Number Generator IP Core User Guide
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User Guides
Embedded

Embedded Peripherals IP User Guide
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Design Examples

Version

DDR3 SDRAM with Board Test System Console

16.0

Intel MAX 10 DDR3 Design with Debug Feature

16.0
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Release Notes

Intel FPGA IP Release Notes
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Training and Videos

Guide for New External Memory Interface (EMIF) Spec Estimator

Intel MAX 10 External Memory Interface (EMIF) Design Guidelines

Intel MAX 10 External Memory Interface Implementation and Debug (Part 1)

Intel MAX 10 External Memory Interface Implementation and Debug (Part 2)
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Intel FPGA Wiki

Design Example - Intel MAX 10 DDR3 300 MHz UniPHY Half Rate x24
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3. Design Planning

Documentation

User Guides / Device Overview / Device Datasheet

Platform Designer User Guide

DSP Builder for Intel FPGAs

Intel MAX 10 FPGA Design Guidelines
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Design Examples

BluePrint Reference Design Part 1

BluePrint Reference Design Part 2
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Training and Videos

Fast & Easy I/O System Design with BluePrint

Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2

Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2

AERP - Intel FPGAs EMIF (External Memory Interfaces) Resources and Pin Planning Tool

Manage device I/Os with the Pin Planner tool in the Quartus II software
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4. Design Entry

Documentation

The Intel Quartus Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Intel Quartus Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Intel Quartus Prime Pro Handbook.

User Guides / Device Overview / Device Datasheet / White Paper

Intel Quartus Prime Standard Edition Handbook Volume 1 Design and Synthesis

Advanced Synthesis Cookbook

Applying the Benefits of Network on a Chip Architecture to FPGA System Design
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Design Examples

Platform Designer Design Examples

Platform Designer Pro Tutorial Design Example for Intel® Arria® 10 FPGA

Platform Designer Tutorial Design Example for Intel Arria 10 FPGA

Platform Designer Tutorial Design Example

VHDL Examples

Verilog Examples

Quartus Design Examples
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Training and Videos

Using the Quartus Prime Software: An Introduction

Introduction to Verilog HDL

Verilog HDL Basics

Advanced Verilog HDL Design Techniques

SystemVerilog with the Quartus II Software

VHDL Basics

Introduction to Platform Designer

Platform Designer in the Intel Quartus Prime Pro Edition Software

Creating a System Design with Platform Designer: Getting Started

Using Spectra-Q Synthesis in the Quartus Prime Software
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Software Downloads

Download center for all versions of the Intel Quartus Prime software
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5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

Simulation Quick-Start for ModelSim-Intel FPGA Edition

Simulating the a8237 Model with the Visual IP Software

Avalon® Verification IP Suite User Guide

Intel FPGA Software Installation and Licensing

Simulating the a8251 Model with the Visual IP Software

Simulating the a8259 Model with the Visual IP Software

Simulating the Reed-Solomon Model with the Visual IP Software

Simulating the Turbo Encoder/Decoder Model with the Visual IP Software

AN 811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Stratix® 10 Devices

AN 720: Simulating the ASMI Block in Your Design

AN 351: Simulating Nios II Processor Designs

AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

Simulating Intel FPGAs Devices with IBIS Models

Simulating Intel FPGA Designs
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Design Examples

Avalon Verification IP Suite Design Example
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Training and Videos

Advanced System Design Using Qsys: System Verification with System Console

Advanced System Design Using Qsys: Component & System Simulation

Avalon Verification Suite

Generating a Testbench with the Intel FPGAs-ModelSim Simulation Tool

How to Set Up RTL Simulations in Quartus, Qsys and Third Party Simulators

Ping Pong PHY DDR3 Simulation
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Intel FPGA Wiki

Simulating Designs with Lower-Level Qsys Systems

Intel Arria 10 EMIF Simulation Guidance

DDR4 Simulation Guidelines

Simpler Chaining DMA Testbench Example
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Software Downloads

Intel FPGA Development Tools

Intel Quartus Software
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6. Implementation and Optimization

Documentation

User Guides / Device Overview / Device Datasheet
Intel® Quartus® Prime Pro and Standard Software User Guides
Intel® MAX® CPLDs and FPGAs
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Training and Videos

The Intel Quartus Prime Software: Foundation (Instructor-led / Virtual Training)

The Quartus Prime Software: Foundation (Standard Edition) (Online Training)
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7. Timing Analysis

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Timing Analysis Overview

Quartus II Scripting Reference Manual

SDC and TimeQuest API Reference Manual

Intel Quartus Prime Timing Analyzer Cookbook

AN 366: Understanding I/O Output Timing for Intel FPGAs Devices

AN 471: High-Performance FPGA PLL Analysis with TimeQuest

AN 433: Constraining and Analyzing Source-Synchronous Interfaces

AN 775: I/O Timing Information Generation Guidelines
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Design Examples

Timing Analyzer Design Examples
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Training and Videos

Getting Started with the TimeQuest Timing Analyzer
Intel® Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer
Intel® Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections
Intel® Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints
Intel® Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces
Intel® Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions
Timing Analysis: Lecture
Timing Analysis: Hands-on Labs
Intel® FPGA Timing Closure: Lecture
Intel® FPGA Timing Closure: Hands-On Lab
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Intel FPGA Wiki

Source Synchronous Interfaces between Intel FPGAs

Source Synchronous Analysis with TimeQuest

Constraining Edge Aligned Source Synch input interfaces in TimeQuest

Constraining Center Aligned Source Synchronous Input Interfaces in TimeQuest

DDR Timing with TimeQuest
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8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Analyzing and Debugging Designs with System Console

Intel FPGAs Virtual JTAG (Intel FPGAs_virtual_jtag) IP Core User Guide

FPGA-Adaptive Software Debug and Performance Analysis

System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug

Intel FPGA USB Download Cable User Guide

Intel FPGA Download Cable II User Guide

EthernetBlaster Communications Cable User Guide

BSDL Support

AN 827: Unified Tool for Generating Programming Files

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files

AN 446: Debugging Nios II Systems with the SignalTap II Logic Analyzer

AN 799: Quick Intel Arria 10 Design Debugging Using Signal Probe and Rapid Recompile

AN 693: Remote Hardware Debugging over TCP/IP for Intel FPGAs SoC

AN 541: SerialLite II Hardware Debugging Guide

AN 543: Debugging Nios II Software Using the Lauterbach Debugger

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

AN 624: Debugging with System Console over TCP/IP
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Training and Videos

Debugging JTAG Chain Integrity

On-Chip Debugging of Memory Interfaces IP in Intel Arria 10 Devices

SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals

The Quartus Software Debug Tools

JTAG Chain Debugger Tool

Quartus In Systems Sources and Probes Debug Flow

U-Boot Console and FDT Debug

Setting Up and Debugging Quartus Floating Licenses

Quartus II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs

Intel Arria 10 Temperature Sensor Debug

Using the Soft Nios processor to Debug Intel Arria 10 External Memory Interfaces

How to Debug Intel FPGAs Triple Speed Ethernet Link Synchronization Issue

Quick Signal Tapping with SignalProbe in the Intel FPGAs Quartus II Software

Understanding and Utilizing USB Blaster and JTAG to Configure Intel FPGAs

Running the SoC Preloader with the ARM* DS-5* Debugger

Intel FPGAs Transceiver Loopback with In-System Sources and Probes

Debugging Techniques for Qsys and Nios Based Bare Metal Systems
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Intel FPGA Wiki

Debug Apps

Development Boards and Kits

DisplayPort MegaCore Debug Checklist

System Console

Low Latency Ethernet 10G MAC Debug Checklist

SDI II MegaCore Debug Checklist

10Gbps Ethernet MAC Debug Checklist

Intel Arria 10 EMIF Debug GUI

Intel Arria 10 Debugging Multiple EMIFs
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Software Downloads
Intel Quartus Prime Software
Intel® FPGA Licensing Support Center
Licensing Questions and Answers

Cable and Adapter Drivers Information
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