Low Latency 100G Ethernet Design Example User Guide

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ID 683371
Date 11/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. LL 100GbE Design Example Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design Example in Hardware
2. LL 100GbE Design Example Description x
2.1. Features 2.2. Software and Hardware Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Design Example Registers
2.4. Design Variations x
2.4.1. Standard CAUI IP Core Variation 2.4.2. CAUI-4 IP Core Variation
1. Quick Start Guide
2. LL 100GbE Design Example Description
A. Document Revision History

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 16.1

The Arria® 10 variations of the LL 100GbE IP core feature a simulatable testbench and a hardware design example that supports compilation and hardware testing, to help you understand usage. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to the Arria® 10 GX Transceiver Signal Integrity Development Kit. The testbench and demonstration design example are available for a wide range of parameters. However, they do not cover all possible parameterizations of the LL 100GbE IP Core.

In addition, for most IP core variations, Intel® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Development Steps for the Design Example
Level Two Title