AN 456: PCI Express High Performance Reference Design

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ID 683541
Date 12/12/2018
Public
Document Table of Contents
Document Table of Contents x
1. PCI Express High Performance Reference Design
1. PCI Express High Performance Reference Design x
1.1. Understanding Throughput in PCI Express 1.2. Deliverables Included with the Reference Design 1.3. Reference Design Functional Description 1.4. Hardware Requirements 1.5. Software Requirements 1.6. Software Installation 1.7. Hardware Installation 1.8. Running the Software Application 1.9. Additional Chaining DMA Commands 1.10. Using SignalTap II 1.11. Performance Benchmarking Results 1.12. Document Revision History
1.1. Understanding Throughput in PCI Express x
1.1.1. Protocol Overhead 1.1.2. Throughput for Posted Writes 1.1.3. Throughput for Reads
1.3. Reference Design Functional Description x
1.3.1. File Naming Conventions 1.3.2. Project Hierarchy
1.7. Hardware Installation x
1.7.1. Programming using the .sof File
1. PCI Express High Performance Reference Design

1. PCI Express High Performance Reference Design

The PCI Express High-Performance Reference Design highlights the performance of the Altera’s PCI Express® products. The design includes a high-performance chaining direct memory access (DMA) that transfers data between the a PCIe Endpoint in the FPGA, internal memory and the system memory. The reference design includes a Windows-based software application that sets up the DMA transfers. The software application also measures and displays the performance achieved for the transfers. This reference design enables you to evaluate the performance of the PCI Express protocol in the following devices:
  • Arria II GX
  • Arria V
  • Arria 10
  • Cyclone IV GX
  • Cyclone V
  • Stratix IV GX
  • Stratix V

Altera offers the IP Compiler for PCI Express IP core in both hard IP and soft IP implementations, and the Arria V, Arria 10, Cyclone V, and Stratix V Hard IP for PCI Express in hard IP. The hard IP implementation is available as a Root Port or Endpoint. Depending on the device used, the hard IP implementation is compliant with PCI Express Base Specification 1.1, 2.0, or 3.0 . The soft IP implementation is available only as an Endpoint. It is compliant with PCI Express Base Specification 1.0a or 1.1 .


Section Content
Understanding Throughput in PCI Express
Deliverables Included with the Reference Design
Reference Design Functional Description
Hardware Requirements
Software Requirements
Software Installation
Hardware Installation
Running the Software Application
Additional Chaining DMA Commands
Using SignalTap II
Performance Benchmarking Results
Document Revision History

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