Verilog Design Examples

The following examples provide instructions for implementing functions using Verilog HDL. For more information on Verilog support, refer to Intel® Quartus® Prime Software Help.

For more examples of Verilog designs for Intel devices, refer to the recommended HDL coding styles chapter of the Intel Quartus Prime Software user guides. You can also access Verilog HDL examples from the language templates in the Intel Quartus Prime software.

Verilog Embedded Processor Functions

• Fast Nios® II Processor Hardware Design Example

Verilog Communications Functions

• POS-PHY LEVEL4 (SPI4.2) Loopback Design on Stratix® III/Stratix® IV Development Board

Verilog Arithmetic Functions

• Adder/Subtractor
• Binary Adder Tree
• Ternary Adder Tree
• Parameterized Counter
• Behavioral Counter
• Gray Counter

Verilog Memory Functions

• Dual Clock Synchronous RAM
• Single Clock Synchronous RAM
• Parameterized RAM with Separate Input and Output Ports
• True Dual-Port RAM with a Single Clock
• Single-Port RAM

Verilog Bus and I/O Functions

• High-Speed Differential I/O Capability
• Tri-State Instantiation
• Bidirectional Pin

Verilog Logic Functions

• 1x64 Shift Register
• 8x64 Shift Register with Taps
• Counter with Asynchronous Reset
• Synchronous State Machine
• Verilog HDL Templates for State Machines

Verilog Digital Signal Processing (DSP) Functions

• Verilog HDL Template for Inferring DSP Blocks in Stratix III and IV FPGAs
• Achieving Unity Gain in Block Floating-Point IFFT+FFT Pair 
• Coefficient Reload for FIR Compiler 
• FFT with 32K-Point Transform Length
• Signed Multiplier with Registered I/O
• Signed Multiplier-Adder
• Unsigned Multiplier
• Unsigned Multipier-Accumulator

Other Verilog Functions

• Creating a Hierarchical Design

How to Use Verilog HDL Examples

Intel provides Verilog HDL design examples as downloadable executable files or displayed as text in your web browser. Select the executable file link to download the file to your hard disk. To use Verilog HDL examples displayed as text in your Intel Quartus Prime software, copy and paste the text from your web browser into the Text Editor. Make sure that the file name of the Verilog HDL design file (.v) corresponds to the entity name in the example. For example, if the entity name is myram, save the file as myram.v.