AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

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ID 683141
Date 11/20/2019
Public
Document Table of Contents
Document Table of Contents x
Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem
Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem x
Supported Configurations for Intel® Stratix® 10 and Intel® Arria® 10 LL 10GbE MAC Designs Clocking and Reset Infrastructure IP Register Mapping Signal Connectivity Differences between Intel® Stratix® 10 and Intel® Arria® 10 Ethernet Design Examples Migration Flow Document Revision History for AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem
Clocking and Reset Infrastructure x
Intel® Stratix® 10 LL 10GbE MAC and Intel® Stratix® 10 Transceiver Native PHY IP Cores Intel® Stratix® 10 LL 10GbE MAC and Intel® Stratix® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Cores
Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

The Low Latency (LL) Ethernet 10G (10GbE) Media Access Controller (MAC) Intel® FPGA IP core includes Intel® Stratix® 10 and Intel® Arria® 10 design examples that are compliant with IEEE 802.3-2008 specification. The interfaces between Intel® Stratix® 10 LL 10GbE MAC Intel® FPGA IP core and physical interface (PHY) IP core are different compared to Intel® Arria® 10 LL 10GbE MAC Intel® FPGA IP core with PHY IP core.

These migration guidelines are meant for those are familiar with Intel® Arria® 10 LL 10GbE MAC Intel® FPGA IP core. Use these migration guidelines if you want to migrate your Intel® Arria® 10 LL 10GbE MAC design to use Intel® Stratix® 10 devices.

Figure 1.  Intel® Stratix® 10 LL 10GbE MAC System
Table 1.  Comparison between Intel® Stratix® 10 and Intel® Arria® 10 Design Examples for LL 10GbE MAC Intel® FPGA IP Core
Design Example MAC Variant PHY Development Kit Intel® Arria® 10 Intel® Stratix® 10
10GBASE-R Ethernet 10G Native PHY (Support L/H-tile Native PHY for Intel® Stratix® 10) Intel® Arria® 10/ Intel® Stratix® 10 GX Transceiver Signal Integrity Yes Yes
1G/2.5G Ethernet with 1588 1G/2.5G 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Arria® 10/ Intel® Stratix® 10 GX Transceiver Signal Integrity Yes Yes
1G/2.5G/10G Ethernet 1G/2.5G/10G 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Arria® 10/ Intel® Stratix® 10 GX Transceiver Signal Integrity Yes Yes
10GBASE-R Register Mode Ethernet 10G Native PHY Intel® Arria® 10 GX Transceiver Signal Integrity Yes Not available
XAUI Ethernet 10G XAUI PHY Intel® Arria® 10 GX FPGA Yes Not available
1G/10G Ethernet 1G/10G 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 GX Transceiver Signal Integrity Yes Not available
1G/10G Ethernet with 1588 1G/10G 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 GX Transceiver Signal Integrity Yes Not available
10M/100M/1G/10G Ethernet 10M/100M/1G/10G 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 GX Transceiver Signal Integrity Yes Not available
10M/100M/1G/10G Ethernet with 1588 10M/100M/1G/10G 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 GX Transceiver Signal Integrity Yes Not available
1G/2.5G Ethernet 1G/2.5G 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Arria® 10 GX Transceiver Signal Integrity Yes Not available
10G USXGMII Ethernet 1G/2.5G/5G/10G (USXGMII) 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Arria® 10 GX Transceiver Signal Integrity Yes Not available
Note: You can access the listed design examples through the LL 10GbE MAC parameter editor in the Intel® Quartus® Prime Pro Edition software.

Section Content
Supported Configurations for Intel Stratix 10 and Intel Arria 10 LL 10GbE MAC Designs
Clocking and Reset Infrastructure
IP Register Mapping
Signal Connectivity Differences between Intel Stratix 10 and Intel Arria 10 Ethernet Design Examples
Migration Flow
Document Revision History for AN 808: Migration Guidelines from Intel Arria 10 to Intel Stratix 10 for 10G Ethernet Subsystem

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