Low Latency 40G Ethernet Example Design User Guide

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ID 683413
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Example Design Description A. Document Revision History
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Example Design in Hardware
2. Example Design Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Variations 2.5. Interface Signals 2.6. Example Design Registers
2.4. Design Variations x
2.4.1. Standard IP Core Variation 2.4.2. 40GBASE-KR4 IP Core Variation
1. Quick Start Guide
2. Example Design Description
A. Document Revision History

1. Quick Start Guide

The Arria 10 variations of the LL 40 GbE IP core feature a simulatable testbench and a hardware example design that supports compilation and hardware testing, to help you understand usage. When you generate the example design, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to the Arria 10 GX Transceiver Signal Integrity Development Kit. The testbench and demonstration example design are available for a wide range of parameters. However, they do not cover all possible parameterizations of the LL 40 GbE IP Core.

In addition, for most IP core variations, Altera provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Development Steps for the Example Design

Section Content
Directory Structure
Design Components
Generating the Design
Simulating the Design
Compiling and Testing the Example Design in Hardware

Level Two Title