Cyclone® 10 FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your Intel® FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

Agilex™ 7 Design Hub Stratix® 10 Developer Center Arria® 10 Developer Center Cyclone® 10 Developer Center MAX® 10 Developer Center

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Intel® Cyclone® 10 GX

Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 GX Transceiver PHY User Guide

Intel Cyclone 10 GX Device Datasheet

Intel Cyclone 10 GX Device Design Guidelines

Intel Cyclone 10 GX Device Errata and Design Guidelines

Intel Cyclone 10 GX Device Overview

Altera® I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide

Intel Cyclone 10 GX Device Family Pin Connection Guidelines

Intel FPGA Advanced SEU Detection IP Core User Guide

Intel Cyclone 10 External Memory Interfaces IP User Guide

Intel Cyclone 10 External Memory Interfaces IP Design Example User Guide

Intel FPGA OCT IP Core User Guide

Intel FPGA GPIO IP Core User Guide

Intel FPGA LVDS SERDES IP Core User Guide

Intel FPGA Temperature Sensor IP Core User Guide

Intel FPGA Parallel Flash Loader IP Core User Guide

Intel FPGA ASMI Parallel II IP Core User Guide

Intel FPGA ASMI Parallel IP Core User Guide

Intel FPGA Remote Update IP Core User Guide

AN 496: Using the Internal Oscillator IP Core

AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families

AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus® Prime Software
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User Guides / Device Overview / Device Datasheet / Application Notes
Intel® Cyclone® 10 LP

Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 LP Device Datasheet

Intel Cyclone 10 LP Device Design Guidelines

Intel Cyclone 10 LP Device Overview

Intel Cyclone 10 LP Device Family Pin Connection Guidelines

LVDS SERDES Transmitter / Receiver IP Cores User Guide

Intel FPGA Parallel Flash Loader IP Core User Guide

Altera® ASMI Parallel II IP Core User Guide

Altera ASMI Parallel IP Core User Guide

Altera Remote Update IP Core User Guide

AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

AN 496: Using the Internal Oscillator IP Core

AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families

AN 731: Simultaneous Switching Noise Guidelines for Intel Cyclone 10 LP, Cyclone IV, and Cyclone III Devices

AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus® Prime Software
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Design Examples
Intel® Cyclone® 10 GX

Intel® Cyclone® 10 GX Design Examples on Design Store
Intel® Cyclone® 10 LP

Intel Cyclone 10 LP Design Examples on Design Store
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Training and Videos
Intel® Cyclone® 10 GX

SEU Mitigation in Intel® FPGA Devices: Hierarchy Tagging
Intel® Cyclone® 10 GX

How to Program Cyclone 10 LP with Two Configuration Images Part 1
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Development Kits
Intel® Cyclone® 10 GX

Intel® Cyclone® 10 GX Development Kit
Intel® Cyclone® 10 GX

Intel® Cyclone 10 LP Evaluation Kit
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Intel FPGA Wiki
Intel®Cyclone® 10 GX

Intel® Cyclone® 10 GX FPLL Reconfiguration
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2. Interface Protocol

Documentation

User Guides
External Memory Interface

Intel® Cyclone® 10 External Memory Interfaces IP User Guide

Intel Cyclone 10 External Memory Interfaces IP Design Example User Guide

Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide
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User Guides / Device Overview / Device Datasheet / Application Notes
Ethernet

Intel® FPGA Triple-Speed Ethernet IP Core User Guide

Intel FPGA Low Latency Ethernet 10G MAC User Guide

Intel Cyclone® 10 GX Transceiver PHY User Guide

Intel FPGA IP for Ethernet - Support Center

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

AN 735: Altera® Low Latency Ethernet 10G MAC IP Core Migration Guidelines

AN 699: Using the Altera Ethernet Design Toolkit
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User Guides
PCI Express*

Intel® Arria® 10 and Intel Cyclone® 10 Avalon®-ST Interface for PCIe* User Guide

Intel Arria 10 or Intel Cyclone 10 Avalon-MM DMA Interface for PCIe Solutions User Guide

Intel Arria 10 and Intel Cyclone 10 Avalon-MM Interface for PCIe User Guide

Intel® Arria 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide

Intel FPGA IP for PCI Express – Support Center
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User Guides
Digital Signal Processing (DSP)

LDPC IP Core User Guide

Intel® FPGA CORDIC IP Core User Guide

BCH IP Core User Guide

FFT IP Core User Guide

FIR II IP Core User Guide

Viterbi IP Core User Guide

Turbo IP Core User Guide

Floating-Point IP Cores User Guide

High-Speed Reed-Solomon IP Core User Guide

Reed-Solomon II IP Core User Guide

NCO IP Core User Guide

Random Number Generator IP Core User Guide
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User Guides
Embedded

Embedded Peripherals IP User Guide
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User Guides
Audio and Video

Intel® FPGA SDI II IP Core User Guide
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Design Examples
PCI Express*

Intel® Arria® 10 and Intel Cyclone® 10 Avalon®-ST Hard IP for PCIe* Design Example User Guide

Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe Design Example User Guide
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Training and Videos
External Memory Interface

Guide for New External Memory Interface (EMIF) Spec Estimator

Steps to Generate Intel® FPGA Cyclone® 10 GX DDR3 Example Design

EMIF Debug Toolkit with Intel Cyclone 10

Automated Check of Intel® FPGA External Memory Interfaces Board Layout Guidelines

Building Parallel Interfaces with Intel® FPGA PHYLite IP

How to Perform Group Pin Placement for PHYLite IP

How to Create the OCT Block for Calibrated Termination I/O Buffer in Altera PHYLIte IP
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Quick Start Videos
Other Serial IP

Intel® FPGA JESD204B IP Quick Start Video
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Intel FPGA Wiki
External Memory Interface

Board Skew Parameter Tool Guide

Automated EMIF Layout Checks
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3. Design Planning

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Getting Started User Guide: Intel Quartus Prime Pro Edition

Platform Designer User Guide (Intel® Quartus® Prime Pro Edition)

DSP Builder for Intel® FPGAs

Intel Cyclone® 10 GX Device Design Guidelines

Intel Cyclone 10 LP Device Design Guidelines
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Design Examples

BluePrint Reference Design Part 1

BluePrint Reference Design Part 2
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Training and Videos

Fast & Easy I/O System Design with BluePrint

Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2

Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2

Intel® FPGA EMIF Resource and Pin Planning (AERP) Tool

Manage Device I/Os with the Pin Planner Tool in the Quartus® II Software
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Intel FPGA Wiki

Intel® FPGA EMIF Resources and Pin Planning Tool
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4. Design Entry

Documentation

The Intel® Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Intel Quartus Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Intel Quartus Prime Pro Handbook.

The Intel® Quartus® Prime design software also comes with Intel® High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for Intel® FPGA products.

User Guides / Device Overview / Device Datasheet / White Paper

Intel Quartus Prime Standard Edition Handbook Volume 1 Design and Synthesis

Design Recommendations User Guide: Intel Quartus Prime Pro Edition

Intel High Level Synthesis Compiler Getting Started Guide

Intel High Level Synthesis Compiler User Guide

Platform Designer User Guide: Intel Quartus Prime Pro Edition

Scripting User Guide: Intel Quartus Prime Pro Edition

Advanced Synthesis Cookbook

Intel High Level Synthesis Compiler Best Practices Guide

Intel High Level Synthesis Compiler Reference Manual

Intel High Level Synthesis Compiler Release Notes

Applying the Benefits of Network on a Chip Architecture to FPGA System Design
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Design Examples

Platform Designer Design Examples

Platform Designer Pro Tutorial Design Example for Intel® Arria® 10 FPGA (.zip)

Platform Designer Tutorial Design Example for Intel Arria 10 FPGA (.zip)

Platform Designer Tutorial Design Example (.zip)

VHDL Examples

Verilog Examples

Quartus® Design Examples
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Training and Videos

Using the Quartus® Prime Software: An Introduction

Introduction to Verilog HDL

Verilog HDL Basics

Advanced Verilog HDL Design Techniques

SystemVerilog with the Quartus II Software

VHDL Basics

Introduction to Platform Designer

Platform Designer in the Intel® Quartus Prime Pro Edition Software

Creating a System Design with Platform Designer: Getting Started

Using Spectra-Q Synthesis in the Quartus Prime Software
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Software Downloads

Download center for all versions of the Intel® Quartus® Prime software
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5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

Simulation Quick-Start for ModelSim*-Intel® FPGA Edition

Simulating the a8237 Model with the Visual IP Software

Avalon® Verification IP Suite User Guide

Intel FPGA Software Installation and Licensing

Simulating the a8251 Model with the Visual IP Software

Simulating the a8259 Model with the Visual IP Software

Simulating the Reed-Solomon Model with the Visual IP Software

Simulating the Turbo Encoder/Decoder Model with the Visual IP Software

AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Intel Stratix® 10 Devices

AN 720: Simulating the ASMI Block in Your Design

AN 351: Simulating Nios® II Processor Designs

AN 508: Cyclone® III Simultaneous Switching Noise (SSN) Design Guidelines

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

Simulating Altera® Devices with IBIS Models

Simulating Intel FPGA Designs
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Design Examples

Avalon® Verification IP Suite Design Example
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Training and Videos

Advanced System Design Using Qsys: System Verification with System Console

Advanced System Design Using Qsys: Component & System Simulation

Design Software Online Demonstration

Avalon® Verification Suite

Verifying Memory Interfaces IP in Arria® 10 Devices

Overview of Mentor Graphic's ModelSim* Software

Generating a Testbench with the Altera-ModelSim Simulation Tool

Simulation of SoC HPS DDR3 Core

How to Set Up RTL Simulations in Quartus, Qsys and Third Party Simulators

Ping Pong PHY DDR3 Simulation
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Intel FPGA Wiki

Simulating Designs with Lower-Level Qsys Systems

Intel® Arria® 10 EMIF Simulation Guidance

DDR4 Simulation Guidelines

Simpler Chaining DMA Testbench Example
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Software Downloads

Intel® FPGA Development Tools

Intel Quartus® Software
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6. Implementation and Optimization

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Intel® Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization

Compiler User Guide: Intel Quartus Prime Pro Edition

Design Optimization User Guide: Intel Quartus Prime Pro Edition

Third-party Synthesis User Guide: Intel Quartus Prime Pro Edition

Design Constraints User Guide: Intel Quartus Prime Pro Edition

Block-Based Design User Guide: Intel Quartus Prime Pro Edition

Partial Reconfiguration User Guide: Intel Quartus Prime Pro Edition

DSP Builder for Intel® FPGAs

Intel Cyclone® 10 GX Device Design Guidelines

Intel Cyclone 10 LP Device Design Guidelines
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Training and Videos

Design Block Reuse in the Intel® Quartus® Prime Pro Software

Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Design Partitioning

Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Introduction

Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Timing Closure & Tips
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7. Timing Analysis

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Timing Analysis Overview

Timing Analyzer User Guide: Intel Quartus Prime Pro Edition

Quartus II Scripting Reference Manual

SDC and TimeQuest API Reference Manual

Intel Quartus Prime Timing Analyzer Cookbook

AN 366: Understanding I/O Output Timing for Altera® Devices

AN 471: High-Performance FPGA PLL Analysis with TimeQuest

AN 433: Constraining and Analyzing Source-Synchronous Interfaces

AN 775: I/O Timing Information Generation Guidelines
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Design Examples

Timing Analyzer Design Examples
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Training and Videos

Getting Started with the TimeQuest Timing Analyzer
Intel® Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer
Intel® Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections
Intel® Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints
Intel® Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces
Intel® Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions
Timing Analysis: Lecture
Timing Analysis: Hands-on Labs
Intel® FPGA Timing Closure: Lecture
Intel® FPGA Timing Closure: Hands-On Lab
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Intel FPGA Wiki

Source Synchronous Interfaces between Intel® FPGAs

Source Synchronous Analysis with TimeQuest

Constraining Edge Aligned Source Synch input interfaces in TimeQuest

Constraining Center Aligned Source Synchronous Input Interfaces in TimeQuest

TimeQuest User Guide

DDR Timing with TimeQuest
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8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Programmer User Guide: Intel Quartus Prime Pro Edition

Debug Tools User Guide: Intel Quartus Prime Pro Edition

Analyzing and Debugging Designs with System Console

Design Debugging Using In-System Sources and Probes

Intel® FPGA Virtual JTAG (Intel® FPGA_virtual_jtag) IP Core User Guide

Analyzing and Debugging Designs with System Console

FPGA-Adaptive Software Debug and Performance Analysis

System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug

ByteBlaster II Download Cable User Guide

Intel FPGA USB Download Cable User Guide

Intel FPGA Download Cable II User Guide

EthernetBlaster Communications Cable User Guide

BSDL Support

AN 827: Unified Tool for Generating Programming Files

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files

AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer

AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile

AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC

AN 541: SerialLite II Hardware Debugging Guide

AN 543: Debugging Nios II Software Using the Lauterbach Debugger

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

AN 624: Debugging with System Console over TCP/IP
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Training and Videos

Debugging JTAG Chain Integrity

On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices

SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals

Intel® Quartus® Software Debug Tools

JTAG Chain Debugger Tool

Quartus In Systems Sources and Probes Debug Flow

U-Boot Console and FDT Debug

Setting Up and Debugging Quartus Floating Licenses

Quartus II Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs

Intel® Arria 10 Temperature Sensor Debug

Using the Soft Nios® processor to Debug Arria 10 External Memory Interfaces

How to Debug Altera® Triple Speed Ethernet Link Synchronization Issue

Quick Signal Tapping with SignalProbe in the Altera Quartus II Software

Understanding and Utilizing USB Blaster and JTAG to Configure Intel FPGAs

Running the SoC Preloader with the ARM* DS-5* Debugger

Altera Transceiver Loopback with In-System Sources and Probes

Debugging Techniques for Qsys and Nios Based Bare Metal Systems
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Intel FPGA Wiki

Debug Apps

Development Boards and Kits

DisplayPort MegaCore Debug Checklist

System Console

Low Latency Ethernet 10G MAC Debug Checklist

SDI II MegaCore Debug Checklist

10Gbps Ethernet MAC Debug Checklist

Intel® Arria® 10 EMIF Debug GUI

Intel® Arria 10 Debugging Multiple EMIFs
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Software Downloads

Intel® FPGA Programming Software

Intel® FPGA Jam™ STAPL Software

Cable and Adapter Drivers Information

MAX+PLUS® II Software

Intel® FPGA Legacy Software

Intel Quartus® Prime Software Stand-Alone Programmer

Intel® FPGA Stand-Alone Programmer Software

Intel Quartus Prime Software
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