AN 809: SerialLite III IP Core Feature and Interface Differences between Stratix 10, Arria 10, and Stratix V

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ID 683797
Date 6/19/2017
Public
Document Table of Contents
Document Table of Contents x
SerialLite III IP Core Feature and Interface Differences between Stratix® 10 and Arria® 10, and Stratix® V
SerialLite III IP Core Feature and Interface Differences between Stratix® 10 and Arria® 10, and Stratix® V x
Differences Summary Revision History
Differences x
Features Clocking IP Core GUI IP Core Signals
SerialLite III IP Core Feature and Interface Differences between Stratix® 10 and Arria® 10, and Stratix® V

SerialLite III IP Core Feature and Interface Differences between Stratix® 10 and Arria® 10, and Stratix® V

SerialLite III Streaming IP core enables high bandwidth, low latency data transfer in chip-to-chip, backplane, and board-to-board interface applications. The IP core utilizes lightweight serial protocol with minimal overhead, providing high data efficiency.

This document summarizes the SerialLite III Streaming IP core differences in Stratix® 10, Arria® 10, and Stratix® V/ Arria® V GZ device families.

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