Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

Intel® Arria® 10 Device Overview

The Intel® Arria® 10 device family consists of high-performance and power-efficient 20 nm mid-range FPGAs and SoCs.

Intel® Arria® 10 device family delivers:

  • Higher performance than the previous generation of mid-range and high-end FPGAs.
  • Power efficiency attained through a comprehensive set of power-saving technologies.

The Intel® Arria® 10 devices are ideal for high performance, power-sensitive, midrange applications in diverse markets.

Table 1.   Sample Markets and Ideal Applications for Intel® Arria® 10 Devices
Market Applications
Wireless
  • Channel and switch cards in remote radio heads
  • Mobile backhaul
Wireline
  • 40G/100G muxponders and transponders
  • 100G line cards
  • Bridging
  • Aggregation
Broadcast
  • Studio switches
  • Servers and transport
  • Videoconferencing
  • Professional audio and video
Computing and Storage
  • Flash cache
  • Cloud computing servers
  • Server acceleration
Medical
  • Diagnostic scanners
  • Diagnostic imaging
Military
  • Missile guidance and control
  • Radar
  • Electronic warfare
  • Secure communications

Section Content
Key Advantages of Intel Arria 10 Devices
Summary of Intel Arria 10 Features
Intel Arria 10 Device Variants and Packages
I/O Vertical Migration for Intel Arria 10 Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Clock Networks and PLL Clock Sources
FPGA General Purpose I/O
External Memory Interface
PCIe Gen1, Gen2, and Gen3 Hard IP
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Low Power Serial Transceivers
SoC with Hard Processor System
Dynamic and Partial Reconfiguration
Enhanced Configuration and Configuration via Protocol
SEU Error Detection and Correction
Power Management
Incremental Compilation
Document Revision History for Intel Arria 10 Device Overview

Related Information
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