ID
683870
Date
7/08/2024
Public
Visible to Intel only — GUID: faq
Ixiasoft
Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides
1.1. FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Flows
1.5. Supported Hardware Description Languages
1.6. Supported Simulation Types
1.7. Supported Simulators
1.8. Post-Fit Simulation Support by FPGA Family
1.9. Automating Simulation with the Run Simulation Feature
1.10. FPGA Simulation Basics Revision History
1.9.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
1.9.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
1.9.2.3. Launching Simulation with the Run Simulation Feature
1.9.2.4. Running RTL Simulation using Run Simulation
1.9.2.5. Output Directories and Files for Run Simulation
Visible to Intel only — GUID: faq
Ixiasoft
Answers to Top FAQs
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
This document is part of a collection. You can download the entire collection as a single PDF: Intel® Quartus® Prime Pro Edition User Guides - Combined PDF link |
What do I need for simulation? |
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What simulators do you support? |
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What are the simulation stages? |
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What are logical libraries? |
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How do I compile into libraries? |
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What is the simulation workflow? |
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How do I automate simulation runs? |
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What are the known issues and limitations? |
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Do you have training on simulation? |