AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Bus LVDS (BLVDS) extends the capability of LVDS point-to-point communication to multipoint configuration. Multipoint BLVDS offers an efficient solution for multipoint backplane applications.
Table 1.  BLVDS Implementation Support in Intel® FPGA DevicesYou can implement BLVDS interfaces in these Intel® devices using the listed I/O standards.
Series Family I/O Standard
Stratix® Intel® Stratix® 10
  • Differential SSTL-18 Class I
  • Differential SSTL-18 Class II
Stratix® V
  • Differential SSTL-2 Class I
  • Differential SSTL-2 Class II
Stratix® IV
Stratix® III
Arria® Intel® Arria® 10
  • Differential SSTL-18 Class I
  • Differential SSTL-18 Class II
Arria® V
  • Differential SSTL-2 Class I
  • Differential SSTL-2 Class II
Arria® II
Cyclone® Intel® Cyclone® 10 GX
  • Differential SSTL-18 Class I
  • Differential SSTL-18 Class II
Intel® Cyclone® 10 LP BLVDS
Cyclone® V
  • Differential SSTL-2 Class I
  • Differential SSTL-2 Class II
Cyclone® IV BLVDS
Cyclone® III LS
Cyclone® III
MAX® Intel® MAX® 10 BLVDS
Note: The programmable drive strength and slew rate features in these devices allow you to customize your multipoint system for maximum performance. To determine the maximum data rate supported, perform a simulation or measurement based on your specific system setup and application.
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