AN 782: Interlaken IP Core Feature and Interface Differences Between Intel® Stratix® 10, Intel® Arria® 10, and Stratix® V Devices
ID
683244
Date
6/12/2017
Public
1. Interlaken IP Core Feature and Interface Differences
Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers at rates from 25 Gbps to 300 Gbps. Intel® FPGA's Interlaken IP solution continues to scale with today’s demand for more bandwidth and higher performance needs.
This application note summarizes the differences between Interlaken IP cores that target the Intel® Stratix® 10, Intel® Arria® 10, and Stratix® V devices.
Device Family | Stratix® V | Intel® Arria® 10 | Intel® Stratix® 10 | ||
---|---|---|---|---|---|
IP Core Variant | 50G Interlaken Intel® FPGA IP Core | 100G Interlaken Intel® FPGA IP Core | 50G Interlaken Intel® FPGA IP Core | 100G Interlaken Intel® FPGA IP Core | Interlaken (2nd Generation) Intel® FPGA IP Core |
Protocol Compliant | Interlaken Protocol Specification, Revision 1.2 | Interlaken Protocol Specification, Revision 1.2 | Interlaken Protocol Specification, Revision 1.2 | Interlaken Protocol Specification, Revision 1.2 | Interlaken Protocol Specification, Revision 1.2 |
Supported Lane x Data Rate (per lane) combinations | 8x6.25 Gbps | 24x6.25 Gbps 12x10.3125 Gbps 12x12.5 Gbps |
8x6.25 Gbps | 24x6.25 Gbps 12x10.3125 Gbps 12x12.5 Gbps |
|
Meta-Frame | 128 - 8192 | 128 - 8192 | 128 - 8192 | 128 - 8192 | 64 - 8192 |
Transceiver Reference Clock Frequency | Multiple | Multiple | Multiple | Multiple | Multiple |
Advanced Error Reporting and Handling | Yes | Yes | Yes | Yes | Yes |
M20K ECC Support | No | Yes | No | Yes | Yes |
Diagnostic Features | No | Yes | No | Yes | Yes |
In-band Flow Control Functionality | Yes | Yes | Yes | Yes | Yes |
Transceiver Native PHY ADME | No | No | Yes | Yes | Yes |
Number of Calender Pages | 1, 2, 4, 8, 16 | 1, 2, 4, 8, 16 | 1, 2, 4, 8, 16 | 1, 2, 4, 8, 16 | 1, 2, 4, 8, 16 |
Transfer Mode Selection | Interleaved Packet |
Interleaved Packet |
Interleaved Packet |
Interleaved Packet |
Interleaved Packet |
Data Format | Single segment | Single segment Dual segment |
Single segment | Single segment Dual segment |
Single segment |
Example Design Support | Simulation | Simulation | Simulation Synthesis |
Simulation Synthesis |
Simulation Synthesis |
Resource Utilization - ALMS | 9800 1 , 2 | 17200 1 , 3 | 9900 2 | 17500 3 | 20100 3 |
Resource Utilization -Logic Registers (Primary - P, Secondary - S) 4 | 20700 (P) 1700 (S) |
34200 (P) 2300 (S) |
20600 (P) 1500 (S) |
34100 (P) 1800 (S) |
38000 (P) 9000 (S) |
Resource Utilization - M20K Blocks | 17 1 , 2 | 38 1 , 3 | 17 2 | 38 3 | 44 3 |
1 For Stratix® V GX devices.
2 IP core variant: 8x6.25
3 IP core variant:12x10.3125
4 Primary registers are the core logic registers; Secondary registers are the implementation, routing and timing closure optimization registers.