Protocol Compliant |
Interlaken Protocol Specification, Revision 1.2 |
Interlaken Protocol Specification, Revision 1.2 |
Interlaken Protocol Specification, Revision 1.2 |
Interlaken Protocol Specification, Revision 1.2 |
Interlaken Protocol Specification, Revision 1.2 |
Supported Lane x Data Rate (per lane) combinations |
8x6.25 Gbps |
24x6.25 Gbps 12x10.3125 Gbps 12x12.5 Gbps |
8x6.25 Gbps |
24x6.25 Gbps 12x10.3125 Gbps 12x12.5 Gbps |
- In devices with L-tile transceivers:
- 4x6.25 Gbps
- 12x10.3125 Gbps
- 12x12.5 Gbps
- In devices with H-tile transceivers:
- 6x25.28 Gbps
- 12x25.28 Gbps
|
Meta-Frame |
128 - 8192 |
128 - 8192 |
128 - 8192 |
128 - 8192 |
64 - 8192 |
Transceiver Reference Clock Frequency |
Multiple |
Multiple |
Multiple |
Multiple |
Multiple |
Advanced Error Reporting and Handling |
Yes |
Yes |
Yes |
Yes |
Yes |
M20K ECC Support |
No |
Yes |
No |
Yes |
Yes |
Diagnostic Features |
No |
Yes |
No |
Yes |
Yes |
In-band Flow Control Functionality |
Yes |
Yes |
Yes |
Yes |
Yes |
Transceiver Native PHY ADME |
No |
No |
Yes |
Yes |
Yes |
Number of Calender Pages |
1, 2, 4, 8, 16 |
1, 2, 4, 8, 16 |
1, 2, 4, 8, 16 |
1, 2, 4, 8, 16 |
1, 2, 4, 8, 16 |
Transfer Mode Selection |
Interleaved Packet |
Interleaved Packet |
Interleaved Packet |
Interleaved Packet |
Interleaved Packet |
Data Format |
Single segment |
Single segment Dual segment |
Single segment |
Single segment Dual segment |
Single segment |
Example Design Support |
Simulation |
Simulation |
Simulation Synthesis |
Simulation Synthesis |
Simulation Synthesis |
Resource Utilization - ALMS |
9800 1 , 2 |
17200 1 , 3 |
9900 2 |
17500 3 |
20100 3 |
Resource Utilization -Logic Registers (Primary - P, Secondary - S) 4 |
20700 (P) 1700 (S) 1 , 2 |
34200 (P) 2300 (S) 1 , 3 |
20600 (P) 1500 (S) 2 |
34100 (P) 1800 (S) 3 |
38000 (P) 9000 (S) 3 |
Resource Utilization - M20K Blocks |
17 1 , 2 |
38 1 , 3 |
17 2 |
38 3 |
44 3 |