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6.1. Synthesis Tool
6.2. Device Resource Reports
6.3. Quartus® Prime Message
6.4. Design Assistant Design Rule Checking
6.5. Timing Constraints and Analysis
6.6. Area and Timing Optimization
6.7. Preserving Performance and Reducing Compilation Time
6.8. Designing with Hyperflex®
6.9. Simulation
6.10. Power Analysis
6.11. Design Implementation, Analysis, Optimization and Verification Revision History
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4.1.2. I/O and LVDS SERDES
Planning and allocating I/O resources is an important task with the high complexity I/O offering in the Agilex™ 5 device. Various considerations are important to effectively plan the available I/O resources to maximize utilization and prevent issues related to signal integrity.
The I/O connection of your FPGA affect the rest of your system and board design, so it is important to plan these connections early in your design cycle.