Visible to Intel only — GUID: oqm1685575804818
Ixiasoft
Visible to Intel only — GUID: oqm1685575804818
Ixiasoft
6.5.1. Recommended Timing Optimization and Analysis Assignments
Number |
Done? |
Checklist item |
---|---|---|
1 |
Turn on Optimize multi-corner timing on the Fitter Settings page in the Settings dialog box. |
|
2 |
Use create_clock and create_generated_clock to specify the frequencies and relationships for all clocks in your design. |
|
3 |
Use set_input_delay and set_output_delay to specify the external device or board timing parameters. |
|
4 |
Use check_timing to generate a report on any problem with the design or applied constraints, including missing constraints. |
|
5 |
Use set_false_path or set_clock_groups for asynchronous paths. |
These assignments and settings are important for large designs such as those in Agilex™ 5 devices.
When you turn on the Optimize multi-corner timing option, the design is optimized to meet its timing requirements at all timing process corners and operating conditions. Therefore, turning on this option helps create a design implementation that is more robust across PVT variations.
In your Timing Analyzer .sdc constraints file, apply the recommended constraints to your design.