Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

4.1.2.3.4. Agilex™ 5 I/O Features

Table 20.   Agilex™ 5 I/O Features Checklist

Number

Done?

Checklist Item

1

 
Check available device HSIO features that can help I/O interfaces:
  • slew rate
  • de-emphasis
  • equalizer
  • calibration
  • I/O delays
  • pseudo open-drain
  • programmable pull-up resistors
  • programmable pre-emphasis
  • VOD

2

 

Consider on-chip termination (OCT) features to save board space in HSIO bank.

3

 

Verify that the required termination scheme is supported for all pin locations in HSIO bank.

4

 

Choose the appropriate mode of DPA, non-DPA, or soft-CDR for high-speed LVDS SERDES interfaces in HSIO bank.

5   Check available device HVIO features that can help I/O interfaces:
  • Programmable current strength
  • Programmable weak pull-up and pull-down resistor
  • Programmable open-drain output
  • Programmable delay chain

The Agilex™ 5 bi-directional I/O element (IOE) features support rapid system integration while simultaneously providing the high bandwidth required to maximize internal logic capabilities and system-level performance. Advanced features for device interfaces assist in high-speed data transfer into and out of the device and reduce the complexity and cost of the PCB.

Intel recommends performing an IBIS or SPICE simulations to optimize your design settings.