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4.1.7. MIPI D-PHY
Number |
Done? |
Checklist item |
---|---|---|
1 |
Identify the number of MIPI D-PHY interface required |
|
2 |
Identify the numbers of data lane per interface |
|
3 |
Understand the data lane implementation from MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs and pin out files |
|
4 |
Review and understand the design guidelines from MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs including the OCT calibration reference |
Before starting the MIPI D-PHY interface design, you need to identify how many MIPI D-PHY interfaces are required in your design and how many data lanes per each interface. By doing so, you can be able to identify how many I/O pins are required in your design for MIPID-PHY. The Agilex™ 5 MIPI D-PHY data lanes and clock lanes are dedicated at fixed pin location; you need to refer to MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs and pin out files to identify the physical pin out location. Apart from that, you also need to refer to the MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs, on the IBIS simulation.