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6.1. Synthesis Tool
6.2. Device Resource Reports
6.3. Quartus® Prime Message
6.4. Design Assistant Design Rule Checking
6.5. Timing Constraints and Analysis
6.6. Area and Timing Optimization
6.7. Preserving Performance and Reducing Compilation Time
6.8. Designing with Hyperflex®
6.9. Simulation
6.10. Power Analysis
6.11. Design Implementation, Analysis, Optimization and Verification Revision History
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4.1.3.4. Clock Outputs
Number |
Done? |
Checklist Item |
---|---|---|
1 |
Check that the PLL offers the required number of clock outputs and use dedicated clock output pins. |
You can connect clock outputs to dedicated clock output pins or dedicated clock networks. I/O PLL can connect to a clock network or a dedicated clock pin.