Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

4.1.3.4. Clock Outputs

Table 23.  Clock Outputs Checklist

Number

Done?

Checklist Item

1

 

Check that the PLL offers the required number of clock outputs and use dedicated clock output pins.

You can connect clock outputs to dedicated clock output pins or dedicated clock networks. I/O PLL can connect to a clock network or a dedicated clock pin.