Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

5.3.3. Board-Level Simulation and Advanced I/O Timing Analysis

Table 42.  Board-Level Simulation and Advanced I/O Timing Analysis Checklist

Number

Done?

Checklist Item

1

 

Perform board-level simulation using IBIS model and IBIS-AMI model.

2

 

Configure board trace models for Quartus® Prime advanced I/O timing analysis.

To ensure that the I/O signaling meets receiver threshold levels on your board setup, perform full board routing simulation with third-party board-level simulation tools using an IBIS model and IBIS-AMI model.

When you include an FPGA device with high-speed interfaces in a board design, knowing the signal integrity and board routing propagation delay is vital for proper system operation. Analyze board level timing as part of the I/O and board planning, especially for high-speed designs.

You can configure board trace models of selected I/O standards and generate “board-aware” signal integrity reports with the Quartus® Prime software. When Enable Advanced I/O Timing is turned on (Timing Analyzer page in the Settings dialog box), the Timing Analyzer uses simulation results for the I/O buffer, package, and the board trace model to generate more accurate I/O delays and extra reports to give insight into signal behavior at the system level. You can use these advanced timing reports as a guide to make changes to the I/O assignments and board design to improve timing and signal integrity.