Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

3.1.4. PLL

Table 9.  PLL Checklist
Number Done? Checklist item
1 Verify the number of PLLs

Verify that your chosen device density package combination includes enough PLLs for your design.