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6.1. Synthesis Tool
6.2. Device Resource Reports
6.3. Quartus® Prime Message
6.4. Design Assistant Design Rule Checking
6.5. Timing Constraints and Analysis
6.6. Area and Timing Optimization
6.7. Preserving Performance and Reducing Compilation Time
6.8. Designing with Hyperflex®
6.9. Simulation
6.10. Power Analysis
6.11. Design Implementation, Analysis, Optimization and Verification Revision History
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3.1.4. PLL
Number | Done? | Checklist item |
---|---|---|
1 | Verify the number of PLLs |
Verify that your chosen device density package combination includes enough PLLs for your design.