Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

4.1.2.3. Agilex™ 5 I/O Features and Pin Connections

Agilex™ 5 I/O pins are designed for ease of use and rapid system integration, while simultaneously providing high bandwidth. Independent modular I/O banks with a common bank structure for vertical migration increase efficiency and flexibility to the high speed I/O.

The following guidelines provide information pertaining to I/O features and pin connections.