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Ixiasoft
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Ixiasoft
4.1.2.3.2. Selectable Standards and Flexible I/O Banks
Number |
Done? |
Checklist Item |
---|---|---|
1 |
Select a suitable signaling type and I/O standard for each I/O pin. The HSIO banks are in the top and bottom I/O bank row. Each I/O bank contains its own PLL, DPA, and SERDES circuitries. |
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2 |
Ensure that the appropriate I/O standard support is supported in the targeted I/O bank. |
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3 |
Place HSIO pins that share voltage levels in the same I/O sub-bank. |
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4 |
Verify that all output signals in each HSIO sub-bank are intended to drive out at the bank’s VCCIO voltage level. |
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5 |
Verify that all voltage-referenced signals in each HSIO lane is sharing the same VREF source. |
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6 |
Check the HSIO bank support for true differential signaling features. |
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7 |
Place I/O pins that share RZQ resistor in the same HSIO bank |
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8 | Select a suitable signaling type and I/O standard for each I/O pin. The HVIO banks are in the bottom left and right shoreline of the device (package dependency). |
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9 | Place HVIO pins that share voltage level in the same HVIO bank. | |
10 | Verify that all output signals in each HVIO bank are intended to drive out at the bank’s VCCIO voltage level. |
Agilex™ 5 HSIO pins are arranged in groups called modular I/O banks. Be sure to use the correct dedicated pin inputs for signals such as clocks and global control signals.
For Agilex™ 5 devices, the board must supply each HSIO sub-bank with one VCCIO_PIO voltage level for every VCCIO_PIO pin in a sub-bank. Each HSIO sub-bank is powered by the VCCIO_PIO pins of that sub-bank and is independent if the VCCIO_PIO pins of other HSIO sub-banks. A single HSIO sub-bank supports single-ended or voltage-referenced output and input signals that are driving and receiving at the same voltage as the VCCIO_PIO. A HSIO sub-bank can simultaneously support any number of input signals with different I/O standards provided that the I/O standard placement adhere to the HSIO design guidelines.
To accommodate voltage-referenced I/O standards, each HSIO sub-bank supports an internal VREF type. Each I/O lane must share the same VREF source. Each I/O sub-bank can only have a single VCCIO_PIO voltage level and each I/O lane must share the same VREF voltage source at a given time. An I/O lane including single-ended or differential standards can support voltage-referenced standards if all voltage-referenced standards use the same VREF source. Voltage-referenced bi-directional and output signals must drive out at the HSIO sub-bank VCCIO_PIO voltage level.
The HSIO bank of Agilex™ 5 device supports 1.3V True Differential Signaling output and 1.05V, 1.1V, 1.2V and 1.3V True Differential Signaling input buffer.
Agilex™ 5 HVIO pins are arranged in groups called High Voltage I/O banks. Be sure to use the correct dedicated pin inputs for signals such as clocks and global control signals.
For Agilex™ 5 devices, the board must supply each HVIO bank with one VCCIO_HVIO voltage level for every VCCIO_HVIO pin in a HVIO bank. Each HVIO bank is powered by the VCCIO_HVIO pins of that sub-bank and is independent if the VCCIO_HVIO pins of other HVIO banks. A single HVIO bank supports single-ended input and output signals that are driving and receiving at the same voltage as the VCCIO_HVIO. A HVIO bank can simultaneously support any number of input signals with different I/O standards provided that the I/O standard placement adhere to the HVIO design guidelines.
For more information, refer to General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs.