Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

4.1.1.1. Partial Reconfiguration

Partial reconfiguration (PR) is supported for Agilex™ 5. PR allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can define multiple personas for a particular region in your design, without impacting operation in areas outside this region. This methodology is effective in systems with multiple functions that time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems.

Figure 1. Partial Reconfiguration Multiple Personas

For more information about Partial Reconfiguration, please refer to Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.