Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

2.5.1. Coding Styles and Design Recommendation

Table 2.  Recommended HDL Coding Styles Checklist
Number Done? Checklist item
1   Follow recommended coding styles, especially for inferring device dedicated logic such as memory and DSP blocks.

HDL coding styles can have a significant effect on the quality of results for programmable logic designs. Use Intel-recommended coding styles to achieve optimal synthesis results. When designing memory and digital system processing (DSP) functions, understand the device architecture so you can take advantage of the dedicated logic block sizes and configurations.

Table 3.  Recommended HDL Coding Styles Checklist
Number Done? Checklist item
1   Use synchronous design practices. Pay attention to clock and reset signals.

In a synchronous design, a clock signal triggers all events. When all of the registers timing requirements are met, a synchronous design behaves in a predictable and reliable manner for all process, voltage, and temperature (PVT) conditions. You can easily target synchronous designs to different device families or speed grades.

For information about Hardware Description Language (HDL) coding style recommendations, refer to the Quartus® Prime Pro Edition User Guide: Design Recommendations.