Visible to Intel only — GUID: rio1685575581116
Ixiasoft
Visible to Intel only — GUID: rio1685575581116
Ixiasoft
5.3.1.1. Unused Pins
Number |
Done? |
Checklist item |
---|---|---|
1 |
Specify the reserved state for unused I/O pins. |
|
2 |
Carefully check the pin connections in the Quartus® Prime software-generated .pin file.
Note: Do not connect RESERVED pins.
|
- As inputs tri-stated
- As output driving ground
- As outputs driving an unspecified signal
- As input tri-stated with bus-hold circuitry
- As input tri-stated with weak pull-up
- The common setting is to set unused pins As inputs tri-stated with weak pull-up.
- To improve signal integrity, set the unused pins to As output driving ground. Doing this reduces inductance by creating a shorter return path and reduces noise on the neighboring I/Os.
Note: Do not use this approach if this results in many paths causing congestion for signals under the device.
- To reduce power dissipation, set clock pins and other unused I/O pins As inputs tri-stated and tie them to GND.
Connection Guidelines for Unused HPS Block
If you are not using the HPS block in the Agilex™ 5 SoC device, you can follow the guidelines below for HPS specific pins:
Pin Function |
If HPS is unused, connect to: |
---|---|
VCCL_HPS VCCL_HPS_CORE0_CORE1 1 VCCL_HPS_CORE21 VCCL_HPS_CORE31 VCCIO_HPS VCCPLL1_HPS VCCPLL2_HPS VCCPLLDIG1_HPS VCCPLLDIG2_HPS |
If you do not intend to utilize the HPS in the Agilex™ 5 SoC device, you must still provide power to the HPS power supplies. For more information, refer to the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs . |
48 HPS Dedicated IO |
No connect (NC) |