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6.1. Synthesis Tool
6.2. Device Resource Reports
6.3. Quartus® Prime Message
6.4. Design Assistant Design Rule Checking
6.5. Timing Constraints and Analysis
6.6. Area and Timing Optimization
6.7. Preserving Performance and Reducing Compilation Time
6.8. Designing with Hyperflex®
6.9. Simulation
6.10. Power Analysis
6.11. Design Implementation, Analysis, Optimization and Verification Revision History
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5.4.2. Configuration Scheme Selection
Number | Done? | Checklist Item |
---|---|---|
1 | Select a configuration scheme to plan companion devices and board connections. |
Agilex™ 5 devices offer several configuration schemes.
You can enable any specific configuration scheme by driving the Agilex™ 5 device MSEL pins to specific values on the board.
Active Serial (AS) configuration scheme uses a serial configuration device, JTAG configuration scheme uses a download cable, and Avalon Streaming ( Avalon® streaming interface) configuration scheme uses an external controller (for example, MAX® ( MAX® II, MAX® V, MAX® 10) devices or a microcontroller).
Warning: If you use Avalon® streaming interface x16 configuration scheme, do not use the I/O pins from bank 3A with pin index [91..95], you need to leave these pins unconnected on the board, you may refer to device pin out files to identify the exact pin location.
Warning: AVST x16 configuration scheme cannot be used in designs that include the HPS. HPS-EMIF and AVST x16 signals are located in the same bank and, therefore, cannot be used simultaneously. The AVST x8 mode uses dedicated SDM I/O pins, which can be used in designs that include the HPS.
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