Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

4.1.2.3.3. Agilex™ 5 Dual-Purpose and Special Pin Connections

Table 19.   Agilex™ 5 Dual-Purpose and Special Pin Connections Checklist

Number

Done?

Checklist Item

1

 

Make dual-purpose pin settings and check for any restrictions when using these pins as regular I/O.

Agilex™ 5 devices allow I/O flexibility with dual-purpose configuration pins. You can use dual-purpose configuration pins as general I/Os after device configuration is complete. Select the desired setting for each of the dual-purpose pins on the Dual-Purpose Pins category of the Device and Pin Options dialog box. Depending on the configuration scheme, these pins can be reserved as regular I/O pins, as inputs that are tri-stated, as outputs that drive ground, or as outputs that drive an unspecified signal.

You can also use dedicated clock inputs, which drive the programmable clock routing networks, as general-purpose I/O pins if they are not used as clock pins. When you use the clock inputs as general inputs, or outputs, I/O registers use ALM-based registers because the clock input pins do not include dedicated I/O registers.

The device-wide reset and clear pins are available as design I/Os if they are not enabled.