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Ixiasoft
Visible to Intel only — GUID: ppy1685575801845
Ixiasoft
6. Design Implementation, Analysis, Optimization and Verification
After you create your design source code and apply constraints including the device selection and timing requirements, your synthesis tool processes the code and maps it to elements of the device architecture. The Quartus® Prime Fitter then performs placement and routing to implement the design elements in specific device resources. If required, you can use the Quartus® Prime software to optimize the design’s resource utilization and achieve timing closure, preserve the performance of unchanged design blocks, and reduce compilation time for future iterations. You can also verify the design functionality with simulation. This section provides guidelines for these stages of the compilation flow.
Section Content
Synthesis Tool
Device Resource Reports
Quartus Prime Message
Design Assistant Design Rule Checking
Timing Constraints and Analysis
Area and Timing Optimization
Preserving Performance and Reducing Compilation Time
Designing with Hyperflex
Simulation
Power Analysis
Design Implementation, Analysis, Optimization and Verification Revision History