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Ixiasoft
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Ixiasoft
3.1.7. MIPI D-DPHY
Number |
Done? |
Checklist item |
---|---|---|
1 |
Understand from data sheet about the DPHY performance per device variant or product group |
|
2 |
Identify the number of interface required and the numbers of data lane per interface because you need to determine the I/O count required |
|
3 |
Review the implementation and design guidelines from Agilex™ 5 FPGA MIPI D-PHY IP User Guide. |
Agilex™ 5 supports MIPI D-PHYv2.5 for both D-Series and E-Series products. This native D-PHY feature support high-speed (HS) and low-power (LP) modes and it allows direct interface with D-PHY compliance component without external components. The D-PHY can perform up to 3.5Gbps per lane. Each HSIO bank can support up to maximum 7 interfaces. The supported data lanes per interface are 1, 2, 4 or 8 with one clock lane. This integrated MIPI D-PHY enabling MIPI CSI-2 and MIPI DSI-2 supports. You need to identify the number of I/O count required per your design implementation.
For more information about the MIPI D-PHY, please refer to MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs.