Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

6.5.2. SDC-on-RTL and Post-Synthesis Static Timing Analysis

Table 69.  SDC-on-RTL and Post-Synthesis Static Timing Analysis Checklist
Number Done? Checklist Item
1 Start Quartus® Prime Pro Edition tool
2 Apply the SDC-on-RTL Constraints by including associated SDC-on-RTL SDC file in the project.
3 Perform Analysis and Elaboration on your design.
4 Run Synthesis and use Post-Synthesis Static Timing Analysis feature to estimate the timing of the design.

Post-Synthesis Static Timing Analysis flow involves running Analysis & Elaboration and Synthesis stages and iterating on your design's static timing analysis results early in the Quartus® Prime Pro Edition software compilation flow without running the Fitter.

The flow is a combination of Synopsys* Design Constraint (SDC) on RTL and post-synthesis static timing analysis. The SDC-on-RTL supports the underlying technology to read the constraints early in the compilation flow and use them in the later stages of the Quartus® Prime Pro Edition compilation.

For more information, refer to the Using Synopsys* Design Constraint (SDC) on RTL Files and Post-Synthesis Static Timing Analysis (STA) sections in the Quartus® Prime Pro Edition User Guide: Design Compilation.