Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

5.1.1.2. Power-Up and Power-Down Sequencing

Table 33.  Power-Up and Power-Down Sequencing Checklist
Number Done? Checklist Item

1

 

Design board for power-up: All Agilex™ 5 GPIO pins are tri-stated until the device is configured and configuration pins drive out. The transceiver pins are at high impedance before the device periphery could get programmed. Once the periphery is programmed, the termination and Vcm are set immediately after transceiver calibration is complete.

2

 

Design voltage power supply ramps to be monotonic.

3

 

Set POR time to ensure power supplies are stable.

4

 

Design power sequencing and voltage regulators for best device reliability. Connect the GND between boards before connecting the power supplies.

5

 

Pull nSTATUS pin high to VCCIO_SDM. Ensure no external component to drive nSTATUS low during power up.

The minimum current requirement for the power-on-reset (POR) supplies must be available during device power-up.
Note: Agilex™ 5 does not support Hot Socketing.

Agilex™ 5 devices have power-up sequencing requirements. You should consider the power-up timing and power-down timing for each rail in order to meet the power sequencing requirements.

All I/O pins in the SDM and the HPS bank, except VSIGP_0, VSIGN_0, VSIGP_1, VSIGN_1, and RREF_SDM are in an undetermined state during device power up and power down.

All HPS data transactions starts after the device is fully powered up.

Input signals of all I/O pins, at any point during power up and power down, cannot exceed the I/O buffer power supply rail of the bank where the I/O pin resides.

When using I/O pins in the HSIO bank, the pin voltage—when the device is not turned on or during power-up or power-down conditions must not exceed VCCIO_PIO or 1.2 V, whichever is lower.

When using I/O pins in the HVIO bank, the pin voltage—when the device is not turned on or during power-up or power-down conditions must not exceed VCCIO_HVIO .

After the device is fully powered up, input signals of the I/O pin cannot exceed the maximum DC input voltage specification as specified in the Agilex™ 5 FPGAs and SoCs Device Data Sheet.