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6.1. Synthesis Tool
6.2. Device Resource Reports
6.3. Quartus® Prime Message
6.4. Design Assistant Design Rule Checking
6.5. Timing Constraints and Analysis
6.6. Area and Timing Optimization
6.7. Preserving Performance and Reducing Compilation Time
6.8. Designing with Hyperflex®
6.9. Simulation
6.10. Power Analysis
6.11. Design Implementation, Analysis, Optimization and Verification Revision History
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4.1.3.3. Clock Feedback Mode
Number |
Done? |
Checklist Item |
---|---|---|
1 |
Ensure you select the correct PLL feedback compensation mode. |
Agilex™ 5 PLLs support six different clock feedback modes, however the fabric-feeding IOPLLs only support three of them. For more information about the supported feedback modes, refer to Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs .
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