Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

2.3.2. HPS IP

The HPS architecture integrates a wide set of peripherals that reduce board size and increase performance within a system. Before evaluating soft IP for the FPGA core, identify which HPS peripherals can be leveraged to save FPGA I/O:
  • EMACs
  • USB controllers
  • I2C controllers
  • I3C controllers
  • UART controllers
  • SPI controllers
  • GPIO interfaces

For more information about the available HPS IP, refer to the Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs.