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6.1. Synthesis Tool
6.2. Device Resource Reports
6.3. Quartus® Prime Message
6.4. Design Assistant Design Rule Checking
6.5. Timing Constraints and Analysis
6.6. Area and Timing Optimization
6.7. Preserving Performance and Reducing Compilation Time
6.8. Designing with Hyperflex®
6.9. Simulation
6.10. Power Analysis
6.11. Design Implementation, Analysis, Optimization and Verification Revision History
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2.3.2. HPS IP
The HPS architecture integrates a wide set of peripherals that reduce board size and increase performance within a system. Before evaluating soft IP for the FPGA core, identify which HPS peripherals can be leveraged to save FPGA I/O:
- EMACs
- USB controllers
- I2C controllers
- I3C controllers
- UART controllers
- SPI controllers
- GPIO interfaces
For more information about the available HPS IP, refer to the Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs.
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