Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 7/15/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

R-Tile Transceiver Performance

Table 47.  R-Tile Transmitter and Receiver Data Rate Performance For specification status, see the Data Sheet Status table
Symbol/Description Condition Transceiver Speed Grade Unit
–1 –2
Supported data rate PCIe* 2.5, 5, 8, 16, 32 2.5, 5, 8, 16, 32 Gbps
CXL 8, 16, 32 — Gbps
Table 48.  R-Tile Slow PLL Performance For specification status, see the Data Sheet Status table
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
VCO frequency PCIe* — 10 — GHz
CXL — — — GHz
PLL bandwidth (BWTX-PKG_PLL1)83 PCIe* 2.5 GT/s 1.5 — 22 MHz
PCIe* 5.0 GT/s 8 — 16 MHz
PLL bandwidth BWTX-PKG_PLL2)83 PCIe* 2.5 GT/s — — — MHz
PCIe* 5.0 GT/s 5 — 16 MHz
PLL peaking (PKGTX-PLL1)83 PCIe* 2.5 GT/s — — 3 dB
PCIe* 5.0 GT/s — — 3 dB
PLL peaking (PKGTX-PLL2)83 PCIe* 2.5 GT/s — — — dB
PCIe* 5.0 GT/s 1 — — dB
Table 49.  R-Tile Fast PLL Performance For specification status, see the Data Sheet Status table
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
VCO frequency PCIe* — 16 — GHz
CXL — 16 — GHz
PLL bandwidth (BWTX-PKG_PLL1)84 PCIe* 8.0 GT/s 0.5 — 4 MHz
PCIe* 16.0 GT/s 0.5 — 4 MHz
PCIe* 32.0 GT/s 0.5 — 1.8 MHz
CXL 8.0 GT/s 0.5 — 4 MHz
CXL 16.0 GT/s 0.5 — 4 MHz
CXL 32.0 GT/s 0.5 — 1.8 MHz
PLL bandwidth (BWTX-PKG_PLL2)84 PCIe* 8.0 GT/s 0.5 — 5 MHz
PCIe* 16.0 GT/s 0.5 — 5 MHz
PCIe* 32.0 GT/s — — — —
CXL 8.0 GT/s 0.5 — 5 MHz
CXL 16.0 GT/s 0.5 — 5 MHz
CXL 32.0 GT/s — — — —
PLL peaking (PKGTX-PLL1)84 PCIe* 8.0 GT/s — — 2 dB
PCIe* 16.0 GT/s — — 2 dB
PCIe* 32.0 GT/s — — 2 dB
CXL 8.0 GT/s — — 2 dB
CXL 16.0 GT/s — — 2 dB
CXL 32.0 GT/s — — 2 dB
PLL peaking (PKGTX-PLL2)84 PCIe* 8.0 GT/s — — 1 dB
PCIe* 16.0 GT/s — — 1 dB
PCIe* 32.0 GT/s — — — —
CXL 8.0 GT/s — — 1 dB
CXL 16.0 GT/s — — 1 dB
CXL 32.0 GT/s — — — —
83 The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.
84 The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.
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