Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 7/15/2024
Public
Document Table of Contents

GPIO-B Differential LVSTL I/O Standards Specifications

Table 28.  GPIO-B Differential LVSTL I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (%)46
Min Typ Max Max Min Max Min Max
LVSTL1147 1.067 1.1 1.133 –0.11 0.11 –0.14 0.14 25
LVSTL10547 1.0185 1.05 1.0815 –0.11 0.11 –0.14 0.14 25
LVSTL700 1.0185 1.05 1.0815 –0.11 0.11 –0.14 0.14 25
46 Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.
47 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire GPIO-B sub-bank is operating in any of the following modes:
  • PHYLITE mode
  • GPIO mode