Visible to Intel only — GUID: rqg1657772206646
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: rqg1657772206646
Ixiasoft
F-Tile Receiver Specifications
Parameter | Symbol | Description | Min | Typical | Max | Unit |
---|---|---|---|---|---|---|
Receiver input eye specifications | VRX-DIFF-PKPK | Receiver input differential peak-to-peak voltage | Closed eye | — | 1,200 | mVdiff-pkpk |
VRX-CM-DC | Receiver input DC common-mode voltage101 | 100 | — | 900 | mV | |
VRX-MAX | Receiver input maximum voltage | — | — | 1,200 | mV | |
VRX-MIN | Receiver input minimum voltage | –200 | — | — | mV | |
TRX-DDJ | Receive input signal data dependent jitter (inter-symbol interference) | — | — | 1 | UIpkpk | |
TRX-RJ | Receive input random jitter | — | — | 0.15 | UIpkpk | |
TRX-PJ | Receive input periodic jitter (at high frequency) | — | — | 0.05 | UIpkpk | |
TRX-TJ | Receive input total jitter (DDJ + RJ + PJ) | — | — | 1 | UIpkpk | |
Equalizer specifications | FPPM-OFFSET | Tolerable data frequency offset | –200 | — | 200 | ppm |
Receiver return loss | ZRL-DIFF-DC | Receiver differential DC return loss | — | — | 10 | dB |
ZRL-DIFF-NYQ | Receiver differential return loss at Nyquist frequency (FBAUD/2) | — | — | 6 | dB | |
ZRL-CM | Receiver common-mode return loss below 10 GHz | — | — | 6 | dB | |
Receiver DC impedance | RDIFF-DC | DC differential receive impedance | 80 | 100 | 120 | Ω |
RCM-DC | DC common-mode receive impedance | 20 | 25 | 30 | Ω |
Parameter | Symbol | Description | Min | Typical | Max | Unit |
---|---|---|---|---|---|---|
Receiver input eye specifications | VRX-DIFF-PKPK | Receiver input differential peak-to-peak voltage102 | Closed eye | — | 1,200 | mV |
VRX-MAX | Receiver input maximum voltage103 | — | — | 1 | V | |
VRX-MIN | Receiver input minimum voltage103 | –0.3 | — | — | V | |
VRX-CM-DC | Receiver input DC common-mode voltage104 | 0 | — | 700 | mV | |
TRX-RJ | Receive input random jitter | — | — | 0.15 | UIpkpk | |
TRX-PJ | Receive input periodic jitter (at high frequency) | — | — | 0.05 | UIpkpk | |
Insertion loss specifications | IINS-LOSS-56Gb/s | Insertion loss at 56 Gbps PAM42/BER <10–4 | — | — | 30 | dB |
IINS-LOSS-53Gb/s | Insertion loss at 53 Gbps PAM42/BER <10–4 | 5105 | — | — | dB | |
IINS-LOSS-30Gb/s | Insertion loss at 32 Gbps NRZ106 /BER <10–12 | — | — | 30 | dB | |
IINS-LOSS-25Gb/s | Insertion loss at 25.78125 Gbps NRZ106/ BER <10–12 | — | — | 30 | dB | |
Receiver return loss | ZRL-DIFF-DC | Receiver differential DC return loss | — | — | 12 | dB |
ZRL-DIFF-NYQ | Receiver differential return loss at Nyquist frequency (FBAUD/2) | — | — | 6 | dB | |
ZRL-CM | Receiver common-mode return loss below 10 GHz | — | — | 6 | dB | |
Receiver DC impedance | RDIFF-DC | DC differential receive impedance | 65 | 85 | 102 | Ω |
80 | 100 | 120 | Ω | |||
RCM-DC | DC common-mode receive impedance | 20 | 25 | 30 | Ω | |
Receiver signal detection107 | VIDLE-THRESH | Receiver signal detect input voltage threshold | 75 | 120 | 175 | mVdiff-pkpk |
101 Referenced to RX GND. This specification is also supported before mode configuration.
102 This is supported when the receiver is powered and configured, powered and unconfigured, or unpowered.
103 VRX_MAX and VRX_MIN are before and after configuration.
104 The specified common-mode range is supported when the receiver is powered and configured, powered and unconfigured, or unpowered. This specification is also supported before mode configuration. If squelch detect is used, receiver DC input common-mode voltage should be within 200 mV to 300 mV. Otherwise, use AC coupling capacitors on board.
105 The minimum insertion loss specification assumes a PAM4 transmitter with 800 mVppd. For transmitters with output amplitude adjustment capabilities and can reduce output amplitude to below 800 mVppd, this minimum insertion loss can be further relaxed.
106 COM compliant package and channel.
107 Receiver signal detection values in this table are applicable to PCIe* and similar standards, such as SATA, where a clock pattern like PCIe* EIEOS 500 MHz clock pattern is used.