Visible to Intel only — GUID: lyn1657772149941
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: lyn1657772149941
Ixiasoft
DSP Block Specifications
Mode | Performance | Unit | ||
---|---|---|---|---|
–1V | –2V | –3V, –3E | ||
Fixed-point 18 × 19 multiplication mode | 900 | 771 | 676 | MHz |
Fixed-point 27 × 27 multiplication mode | 900 | 771 | 676 | MHz |
Fixed-point 18 × 19 multiplier adder mode61 | 900 | 771 | 676 | MHz |
Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode | 900 | 771 | 676 | MHz |
Fixed-point four 9 × 9 multiplier adder mode | 900 | 771 | 676 | MHz |
Fixed-point 18 × 19 systolic mode | 900 | 771 | 676 | MHz |
Fixed-point 18 × 19 complex multiplication mode | 900 | 771 | 676 | MHz |
FP32 floating-point multiplication mode | 750 | 579 | 507 | MHz |
FP32 floating-point adder or subtract mode | 750 | 579 | 507 | MHz |
FP32 floating-point multiplier adder or subtract mode | 750 | 579 | 507 | MHz |
FP32 floating-point multiplier accumulate mode | 750 | 579 | 507 | MHz |
Addition or subtraction of two FP16 floating-point multiplication mode | 750 | 579 | 507 | MHz |
Sum/sub of two FP16 multiplications with FP32 (addition/subtraction) | 750 | 579 | 507 | MHz |
Sum/sub of two FP16 multiplications with accumulation (addition/subtraction) | 750 | 579 | 507 | MHz |
FP32 floating-point complex multiplication | 750 | 579 | 507 | MHz |
FP32 floating-point vector dot product | 750 | 579 | 507 | MHz |
FP16 floating-point complex multiplication | 750 | 579 | 507 | MHz |
FP16 floating-point vector dot product | 750 | 579 | 507 | MHz |
61 When Chainout is enabled to send data to the next DSP but systolic registers are not used, the performance specifications for the following speed grades are as follows:
- –1V: 675 MHz
- –2V: 578 MHz
- –3V and –3E: 507 MHz