Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 7/15/2024
Public
Document Table of Contents

DSP Block Specifications

Table 33.  DSP Block Performance Specifications For specification status, see the Data Sheet Status table
Mode Performance Unit
–1V –2V –3V, –3E
Fixed-point 18 × 19 multiplication mode 900 771 676 MHz
Fixed-point 27 × 27 multiplication mode 900 771 676 MHz
Fixed-point 18 × 19 multiplier adder mode61 900 771 676 MHz
Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode 900 771 676 MHz
Fixed-point four 9 × 9 multiplier adder mode 900 771 676 MHz
Fixed-point 18 × 19 systolic mode 900 771 676 MHz
Fixed-point 18 × 19 complex multiplication mode 900 771 676 MHz
FP32 floating-point multiplication mode 750 579 507 MHz
FP32 floating-point adder or subtract mode 750 579 507 MHz
FP32 floating-point multiplier adder or subtract mode 750 579 507 MHz
FP32 floating-point multiplier accumulate mode 750 579 507 MHz
Addition or subtraction of two FP16 floating-point multiplication mode 750 579 507 MHz
Sum/sub of two FP16 multiplications with FP32 (addition/subtraction) 750 579 507 MHz
Sum/sub of two FP16 multiplications with accumulation (addition/subtraction) 750 579 507 MHz
FP32 floating-point complex multiplication 750 579 507 MHz
FP32 floating-point vector dot product 750 579 507 MHz
FP16 floating-point complex multiplication 750 579 507 MHz
FP16 floating-point vector dot product 750 579 507 MHz
61 When Chainout is enabled to send data to the next DSP but systolic registers are not used, the performance specifications for the following speed grades are as follows:
  • –1V: 675 MHz
  • –2V: 578 MHz
  • –3V and –3E: 507 MHz